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IDT74FCT821B 데이터시트 PDF




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부품번호 IDT74FCT821B 기능
기능 HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
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IDT74FCT821B 데이터시트, 핀배열, 회로
®
Integrated Device Technology, Inc.
HIGH-PERFORMANCE
CMOS BUS INTERFACE
REGISTERS
IDT54/74FCT821A/B/C
IDT54/74FCT823A/B/C
IDT54/74FCT824A/B/C
IDT54/74FCT825A/B/C
FEATURES:
• Equivalent to AMD’s Am29821-25 bipolar registers in
pinout/function, speed and output drive over full tem-
perature and voltage supply extremes
• IDT54/74FCT821A/823A/824A/825A equivalent to
FASTspeed
• IDT54/74FCT821B/823B/824B/825B 25% faster than
FAST
• IDT54/74FCT821C/823C/824C/825C 40% faster than
FAST
• Buffered common Clock Enable (EN) and asynchronous
Clear input (CLR)
• IOL = 48mA (commercial) and 32mA (military)
• Clamp diodes on all inputs for ringing suppression
• CMOS power levels (1mW typ. static)
• TTL input and output compatibility
• CMOS output level compatible
• Substantially lower input current levels than AMD’s
bipolar Am29800 series (5µA max.)
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT54/74FCT800 series is built using an advanced
dual metal CMOS technology.
The IDT54/74FCT820 series bus interface registers are
designed to eliminate the extra packages required to buffer
existing registers and provide extra data width for wider
address/data paths or buses carrying parity. The IDT54/
74FCT821 are buffered, 10-bit wide versions of the popular
‘374 function. The IDT54/74FCT823 and IDT54/74FCT824
are 9-bit wide buffered registers with Clock Enable (EN) and
Clear (CLR) – ideal for parity bus interfacing in high-perform-
ance microprogrammed systems. The IDT54/74FCT825 are
8-bit buffered registers with all the ‘823 controls plus multiple
enables (OE1, OE2, OE3) to allow multiuser control of the
interface, e.g., CS, DMA and RD/WR. They are ideal for use
as an output port requiring HIGH IOL/IOH.
All of the IDT54/74FCT800 high-performance interface
family are designed for high-capacitance load drive capability,
while providing low-capacitance bus loading at both inputs
and outputs. All inputs have clamp diodes and all outputs are
designed for low-capacitance bus loading in high-impedance
state.
FUNCTIONAL BLOCK DIAGRAMS
IDT54/74FCT821/823/825
D0 DN
EN
IDT54/74FCT824
D0
EN
DN
CLR
CP
D CL Q
CP Q
D CL Q
CP Q
CLR
CP
OE
Y0
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor Co.
YN
2608 cnv* 01
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1992 Integrated Device Technology, Inc.
7.19
OE
D CL Q
CP Q
D CL Q
CP Q
Y0 YN
2608 cnv* 02
MAY 1992
DSC-4618/2
1




IDT74FCT821B pdf, 반도체, 판매, 대치품
IDT54/74FCT821/823/824/825A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Rating
Commercial
VTERM(2) Terminal Voltage
with Respect to
GND
VTERM(3) Terminal Voltage
with Respect to
GND
–0.5 to +7.0
–0.5 to VCC
TA Operating
0 to +70
Temperature
TBIAS Temperature
–55 to +125
Under Bias
TSTG Storage
–55 to +125
Temperature
PT
Power Dissipation
0.5
Military
–0.5 to +7.0
–0.5 to VCC
–55 to +125
–65 to +135
–65 to +150
0.5
Unit
V
V
°C
°C
°C
W
Symbol Parameter(1) Conditions Typ. Max. Unit
CIN Input
VIN = 0V
6 10 pF
Capacitance
COUT Output
VOUT = 0V
8 12 pF
Capacitance
NOTE:
2608 tbl 05
1. This parameter is measured at characterization but not tested.
IOUT
DC Output
Current
120 120 mA
NOTES:
2608 tbl 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed VCC by +0.5V unless otherwise noted.
2. Input and VCC terminals only.
3. Outputs and I/O terminals only.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = VCC – 0.2V
Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%
Symbol
Parameter
Test Conditions(1)
Min. Typ.(2)
VIH Input HIGH Level
Guaranteed Logic HIGH Level
2.0 —
Max.
Unit
V
VIL Input LOW Level
Guaranteed Logic LOW Level
— — 0.8 V
II H Input HIGH Current
II L Input LOW Current
VCC = Max.
VI = VCC
VI = 2.7V
VI = 0.5V
— — 5 µA
— — 5(4)
— — –5(4)
VI = GND
— — –5
IOZH
IOZL
Off State (High Impedance)
Output Current
VCC = Max.
VO = VCC
VO = 2.7V
VO = 0.5V
— — 10 µA
— — 10(4)
— — –10(4)
VO = GND
— — –10
VIK Clamp Diode Voltage
IOS Short Circuit Current
VCC = Min., IN = –18mA
VCC = Max.(3), VO = GND
— –0.7 –1.2 V
–75 –120 — mA
VOH Output HIGH Voltage
VCC = 3V, VIN = VLC or VHC, IOH = –32µA
VCC = Min.
IOH = –300µA
VHC
VHC
VCC
VCC
V
VIN = VIH or VIL
IOH = –15mA MIL.
2.4 4.3 —
IOH = –24mA COM'L. 2.4 4.3
VOL Output LOW Voltage
VCC = 3V, VIN = VLC or VHC, IOL = 300µA
VCC = Min.
IOL = 300µA
— GND VLC
V
— GND VLC(4)
VIN = VIH or VIL
IOL = 32mA MIL.
— 0.3 0.5
IOL = 48mA COM'L.
— 0.3 0.5
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
2608 tbl 06
7.19 4

4페이지










IDT74FCT821B 전자부품, 판매, 대치품
IDT54/74FCT821/823/824/825A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
VCC 7.0V
VIN
Pulse
Generator
V OUT
D.U.T.
500
50pF
500
RT CL
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCH POSITION
Test
Switch
Open Drain
Disable Low
Enable Low
Closed
All Other Tests
Open
DEFINITIONS:
2608 tbl 09
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
t SU
t SU
tH
t REM
tH
PULSE WIDTH
3V
1.5V
0V
3V
1.5V
0V
LOW-HIGH-LOW
PULSE
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
3V
1.5V
0V
1.5V
tW
1.5V
PROPAGATION DELAY
SAME PHASE
INPUT TRANSITION
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
tPLH
t PLH
t PHL
tPHL
3V
1.5V
0V
VOH
1.5V
VOL
3V
1.5V
0V
ENABLE AND DISABLE TIMES
ENABLE
CONTROL
INPUT
OUTPUT
NORMALLY
LOW
t PZL
SWITCH
CLOSED
t PZH
OUTPUT SWITCH
NORMALLY OPEN
HIGH
3.5V
1.5V
1.5V
0V
DISABLE
tPLZ
3V
1.5V
0V
3.5V
t PHZ
0.3V V OL
0.3V V OH
0V
NOTES
2608 drw 01
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate 1.0 MHz; ZO 50; tF 2.5ns;
tR 2.5ns.
7.19 7

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