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NT4GC72B4PB0NL 데이터시트 PDF




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부품번호 NT4GC72B4PB0NL 기능
기능 Registered DDR3 SDRAM DIMM
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NT4GC72B4PB0NL 데이터시트, 핀배열, 회로
NT2GC72B89B0NJ/NT2GC72B89B2NJ/NT2GC72C89B0NJ/NT2GC72C89B2NJ
NT4GC72B4PB0NL/NT4GC72C4PB0NL/NT4GC72C4PB2NL/NT4GC72B8PB0NL/NT4GC72C8PB0NL/NT4GC72C8PB2NL
NT8GC72B4NB1NJ/NT8GC72B4NB3NJ/NT8GC72C4NB1NJ/NT8GC72C4NB3NJ
NT16TC72B4NB1NL/NT16TC72C4NB1NL/NT16TC72C4NB3NL
2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 / 16GB: 2G x 72
PC3-8500 / PC3-10600
Registered DDR3 SDRAM DIMM
Based on DDR3-1066/1333 256Mx8 (2GB/4GB) / 512Mx4 (4GB/8GB) SDRAM B-Die
Based on DDR3-1066 1Gx4 (DDP) (16GB) SDRAM B-Die
Features
•Performance:
Speed Sort
PC3-8500 PC3-10600
-BE -CG Unit
DIMM CAS Latency
79
fck Clock Frequency
533 667 MHz
tck Clock Cycle
1.875
1.5 ns
fDQ DQ Burst Frequency 1066
1333
Mbps
240-Pin Registered Dual In-Line Memory Module (RDIMM)
2GB/4GB: 256Mx72/512Mx72 DDR3 Registered DIMM based on
256Mx8 DDR3 SDRAM B-Die devices
4GB/8GB: 512Mx72/1024Mx72 DDR3 Registered DIMM based
on 512Mx4 DDR3 SDRAM B-Die devices
16GB: 2Gx72 DDR3 Registered DIMM based on 1024Mx4 (DDP)
DDR3 SDRAM B-Die devices
Intended for 533MHz/667MHz applications
• Inputs and outputs are SSTL-15 compatible
VDD = VDDQ = 1.5V ± 0.075V (for DDR3)
VDD = VDDQ = 1.35V -0.0675/+0.1V (for DDR3L)
• SDRAMs have 8 internal banks for concurrent operation
• Differential clock inputs
• Data is read or written on both clock edges
DRAM DLL aligns DQ and DQS transitions with clock transitions.
Address and control signals are fully synchronous to positive
clock edge
Nominal and Dynamic On-Die Termination support
• Programmable Operation:
- DIMM  Latency: 6,7,8,9
- Burst Type: Sequential or Interleave
- Burst Length: BC4, BL8
- Operation: Burst Read and Write
Two different termination values (Rtt_Nom & Rtt_WR)
15/10/1 (row/column/rank) Addressing for 2GB
15/11/1 (row/column/rank) Addressing for 4GB (512Mx4 Device)
15/10/2 (row/column/rank) Addressing for 4GB (256Mx8 Device)
15/11/2 (row/column/rank) Addressing for 8GB
15/11/4 (row/column/rank) Addressing for 16GB
Extended operating temperature rage
Auto Self-Refresh option
• Serial Presence Detect
• Gold contacts
SDRAMs are in 78-ball BGA Package
RoHS compliance and Halogen free
Description
NT2GC72B89B0NJ, NT2GC72B89B2NJ, NT2GC72C89B0NJ, NT2GC72C89B2NJ, NT4GC72B4PB0NL, NT4GC72C4PB0NL,
NT4GC72C4PB2NL, NT4GC72B8PB0NL ,NT4GC72C8PB0NL , NT4GC72C8PB2NL, NT8GC72B4NB1NJ,
NT8GC72B4NB3NJ ,NT8GC72C4NB1NJ, NT8GC72C4NB3NJ, NT16TC72B4NB1NL, NT16TC72C4NB1NL and NT16TC72C4NB3NL
are 240-Pin Double Data Rate 3 (DDR3) Synchronous DRAM Registered Dual In-Line Memory Module, organized as one rank of
256Mx72 (2GB), one rank or two ranks of 512Mx72 (4GB), two ranks of 1Gx72 (8GB) and four ranks of 2Gx72 (16GB) high-speed memory
array. Modules use nine 256Mx8 (2GB) 78-ball BGA packaged devices, eighteen 256Mx8 (4GB) 78-ball BGA packaged devices, thirty-six
512Mx4 (8GB) 78-ball BGA packaged devices and thirty-six 1Gx4 (DDP) (16GB) 78-ball BGA packaged devices. These DIMMs are
manufactured using raw cards developed for broad industry use as reference designs. The use of these common design files minimizes
electrical variation between suppliers. All NANYA DDR3 SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25”
long space-saving footprint.
The DIMM is intended for use in applications operating of 533MHz/667MHz clock speeds and achieves high-speed data transfer rates of
1066Mbps/1333Mbps. Prior to any access operation, the device  latency and burst/length/operation type must be programmed into the
DIMM by address inputs A0-A14 and I/O inputs BA0~BA2 using the mode register set cycle.
The DIMM uses serial presence-detect implemented via a serial EEPROM using a standard IIC protocol. The first 128 bytes of SPD data
are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer.
REV 1.2
12/2010
1
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.




NT4GC72B4PB0NL pdf, 반도체, 판매, 대치품
NT2GC72B89B0NJ/NT2GC72B89B2NJ/NT2GC72C89B0NJ/NT2GC72C89B2NJ
NT4GC72B4PB0NL/NT4GC72C4PB0NL/NT4GC72C4PB2NL/NT4GC72B8PB0NL/NT4GC72C8PB0NL/NT4GC72C8PB2NL
NT8GC72B4NB1NJ/NT8GC72B4NB3NJ/NT8GC72C4NB1NJ/NT8GC72C4NB3NJ
NT16TC72B4NB1NL/NT16TC72C4NB1NL/NT16TC72C4NB3NL
2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 / 16GB: 2G x 72
PC3-8500 / PC3-10600
Registered DDR3 SDRAM DIMM
Input/Output Functional Description
Symbol
Type Polarity
Function
CK0, CK1
, 
Input
Cross
point
The system clock inputs. All address and command lines are sampled on the cross point of the
rising edge of CK and falling edge of . A Delay Locked Loop (DLL) circuit is driven from the
clock inputs and output timing for read operations is synchronized to the input clock. However,
CK1 and  are terminated but not used on RDIMMs.
CKE0, CKE1
Input
Active Activates the DDR3 SDRAM CK signal when high and deactivates the CK signal when low. By
High deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode.
 
Input
Active
Low
Enable the command decoders for the associated rank of SDRAM when low and disables
decoders when high. When decoders are disabled, new commands are ignored and previous
operations continue. Other combinations of these input signals perform unique functions,
including disabling all outputs (except CKE and ODT) of the register(s) on the DIMM or accessing
internal control words in the register device(s). For modules with two registers,  and  operate
similarly to  and  for the second set of register outputs or register control words.
, , 
ODT0, ODT1
Input
Input
Active
Low
Active
High
When sampled at the positive rising edge of CK and falling edge of , signals , , 
define the operation to be executed by the SDRAM.
Asserts on-die termination for DQ, DM, DQS, and  signals if enabled via the DDR3 SDRAM
mode register.
DM0 DM8
Input
Active
High
The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask
by allowing input data to be written if it is low but blocks the write operation if it is high. In Read
mode, DM lines have no effect.
DQS0 DQS17
 
I/O
TDQS9 TDQS17
 
Output
Cross
point
The data strobes, associated with one data byte, sourced with data transfers. In Write mode, the
data strobe is sourced by the controller and is centered in the data window. In Read mode, the
data strobe is sourced by the DDR3 SDRAM and is sent at the leading edge of the data window.
 signals are complements, and timing is relative to the cross point of respective DQS and
. If the module is to be operated in single ended strobe mode, all  signals must be tied on
the system board to VSS and DDR3 SDRAM mode registers programmed appropriately.
TDQS/ is applicable for x8 DRAMs only. When enabled via mode register A11=1 in MR1,
DRAM will enable the same termination resistance function on TDQS/ that is applied to
DQS/. When disabled via mode register A11=0 in MR1, DM/TDQS will provide the data
mask function  is not used. X4/x16 DRAMs must disable the TDQS function via mode
register A11=0 in MR1.
BA0, BA1, BA2 Input
- Selects which DDR3 SDRAM internal bank of four or eight is activated.
A0 A9
A10/AP
A11
A12/
A13
Input
DQ0 DQ63
Input
During a Bank Activate command cycle, defines the row address when sampled at the cross point
of the rising edge of CK and falling edge of . During a Read or Write command cycle, defines
the column address when sampled at the cross point of the rising edge of CK and falling edge of
. In addition to the column address, AP is used to invoke autoprecharge operation at the end of
- the burst read or write cycle. If AP is high, autoprecharge is selected and BA0-BAn defines the
bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command
cycle, AP is used in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is
high, all banks will be precharged regardless of the state of BA0-BAn inputs. If AP is low, then
BA0-BAn are used to define which bank to precharge.
- Data Input/Output pins.
CB0 CB7 I/O - Check bits are used for ECC.
VDD, VDDSPD, VSS
VREFDQ, VREFCA
Supply
Supply
SDA
I/O
- Power supplies for core, I/O, Serial Presence Detect, Temp sensor, and ground for the module.
- Reference voltage for SSTL15 inputs.
This is a bidirectional pin used to transfer data into or out of the SPD EEPROM and temp sensor.
- A resistor must be connected from the SDA bus line to VDDSPD on the system planar to act as a pull
up.
SCL
SA0 SA2


Par_In
Input
Input
Output
Input
Input
- This signal is used to clock data into and out of the SPD EEPROM and Temp sensor.
- Address pins used to select the Serial Presence Detect and Temp sensor base address.
- The  pin is reserved for use to flag critical module temperature.
- This signal resets the DDR3 SDRAM.
- Parity bit for the Address and Control bus.

Output
-
Parity error detected on the Address and Control bus. A resistor may be connected from bus line
to VDD on the system planar to act as a pull up.
REV 1.2
12/2010
4
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.

4페이지










NT4GC72B4PB0NL 전자부품, 판매, 대치품
NT2GC72B89B0NJ/NT2GC72B89B2NJ/NT2GC72C89B0NJ/NT2GC72C89B2NJ
NT4GC72B4PB0NL/NT4GC72C4PB0NL/NT4GC72C4PB2NL/NT4GC72B8PB0NL/NT4GC72C8PB0NL/NT4GC72C8PB2NL
NT8GC72B4NB1NJ/NT8GC72B4NB3NJ/NT8GC72C4NB1NJ/NT8GC72C4NB3NJ
NT16TC72B4NB1NL/NT16TC72C4NB1NL/NT16TC72C4NB3NL
2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 / 16GB: 2G x 72
PC3-8500 / PC3-10600
Registered DDR3 SDRAM DIMM
Functional Block Diagram (Part 1 of 2)
[4GB 2 Ranks, 256Mx8 DDR3 SDRAMs]
DQS8

DM8/DQS17

CB[7:0]
DQS

TDQS

DQ[7:0]
ZQ
D8
DQS

TDQS

DQ[7:0]
ZQ
D17
DQS4

DM4/DQS13

DQ[39:32]
DQS

TDQS

DQ[7:0]
ZQ
D4
DQS

TDQS

DQ[7:0]
ZQ
D13
DQS3

DM3/DQS12

DQ[31:24]
DQS

TDQS

DQ[7:0]
ZQ
D3
DQS

TDQS

DQ[7:0]
ZQ
D12
DQS5

DM5/DQS14

DQ[47:40]
DQS

TDQS

DQ[7:0]
ZQ
D5
DQS

TDQS

DQ[7:0]
ZQ
D14
DQS2

DM2/DQS11

DQ[23:16]
DQS

TDQS

DQ[7:0]
ZQ
D2
DQS

TDQS

DQ[7:0]
ZQ
D11
DQS6

DM6/DQS15

DQ[55:48]
DQS

TDQS

DQ[7:0]
ZQ
D6
DQS

TDQS

DQ[7:0]
ZQ
D15
DQS1

DM1/DQS10

DQ[15:8]
DQS

TDQS

DQ[7:0]
ZQ
D1
DQS

TDQS

DQ[7:0]
ZQ
D10
DQS7

DM7/DQS16

DQ[63:56]
DQS

TDQS

DQ[7:0]
ZQ
D7
DQS

TDQS

DQ[7:0]
ZQ
D16
DQS0

DM0/DQS9

DQ[7:0]
DQS

TDQS

DQ[7:0]
ZQ
D0
DQS

TDQS

DQ[7:0]
ZQ
D9
Vtt
Vtt
Notes :
1. DQ-to-I/O wiring is shown as recommended but may be changed.
2. ZQ resistors are 240Ω ± 1%. For all other resistor values refer to the appropriate wiring diagram.
3. Unless otherwise noted, resistor values are 15Ω ± 5%.
4. See the wiring diagrams for all resistors associated with the command, address and control bus.
VDDSPD
VDD
VTT
VREFCA
VREFDQ
VSS
SPD
D0-D17
D0-D17
D0-D17
D0-D17
D0-D17
SCL
SA0
SA1
SA2
SPD w/ Integrated Thermal Sensor
SCL
A0
A1
A2


SDA
REV 1.2
12/2010
7
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.

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NT4GC72B4PB0NL

Registered DDR3 SDRAM DIMM

Nanya Technology
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NT4GC72B4PB0NL-CG

Registered DDR3 SDRAM DIMM

Nanya Technology
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