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기능 240pin Registered DIMM
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M393B2G73AH0 데이터시트, 핀배열, 회로
Rev. 1.0, Jul. 2010
M393B2G70AH0
M393B2G73AH0
M393B4G70AM0
240pin Registered DIMM
based on 4Gb A-die
78FBGA with Lead-Free & Halogen-Free
(RoHS compliant)
1.35V
datasheet
SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND
SPECIFICATIONS WITHOUT NOTICE.
Products and specifications discussed herein are for reference purposes only. All information discussed
herein is provided on an "AS IS" basis, without warranties of any kind.
This document and all information discussed herein remain the sole and exclusive property of Samsung
Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property
right is granted by one party to the other party under this document, by implication, estoppel or other-
wise.
Samsung products are not intended for use in life support, critical care, medical, safety equipment, or
similar applications where product failure could result in loss of life or personal or physical harm, or any
military or defense application, or any governmental procurement to which special terms or provisions
may apply.
For updates or additional information about Samsung products, contact your nearest Samsung office.
All brand names, trademarks and registered trademarks belong to their respective owners.
2010 Samsung Electronics Co., Ltd. All rights reserved.
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M393B2G73AH0 pdf, 반도체, 판매, 대치품
Registered DIMM
datasheet
Rev. 1.0
DDR3L SDRAM
1. DDR3L Registered DIMM Ordering Information
Part Number2
Density
Organization
M393B2G70AH0-YF7/F8/H9
M393B2G73AH0-YF7/F8/H9
M393B4G70AM0-YF7/F8/H9
16GB
16GB
32GB
2Gx72
2Gx72
4Gx72
NOTE :
1. "##" - F7/F8/H9
2. F7(800Mbps 6-6-6) / F8(1066Mbps 7-7-7) / H9(1333Mbps 9-9-9)
- DDR3-1333(9-9-9) is backward compatible to DDR3-1066(7-7-7) DDR3-800(6-6-6)
- DDR3-1066(7-7-7) is backward compatible to DDR3-800(6-6-6)
Component Composition
1Gx4(K4B4G0446A-HY##)*36
512Mx8(K4B4G0846A-HY##)*36
DDP 2Gx4(K4B8G0446A-MY##)*36
Number of
Rank
2
4
4
Height
30mm
30mm
30mm
2. Key Features
Speed
tCK(min)
CAS Latency
tRCD(min)
tRP(min)
tRAS(min)
tRC(min)
DDR3-800
6-6-6
2.5
6
15
15
37.5
52.5
DDR3-1066
7-7-7
1.875
7
13.125
13.125
37.5
50.625
DDR3-1333
9-9-9
1.5
9
13.5
13.5
36
49.5
Unit
ns
nCK
ns
ns
ns
ns
• JEDEC standard 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V) Power Supply
• VDDQ = 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V)
• 400MHz fCK for 800Mb/sec/pin, 533MHz fCK for 1066Mb/sec/pin, 667MHz fCK for 1333Mb/sec/pin
• 8 independent internal bank
• Programmable CAS Latency: 6,7,8,9
• Programmable Additive Latency(Posted CAS) : 0, CL - 2, or CL - 1 clock
• Programmable CAS Write Latency(CWL) = 5(DDR3-800), 6(DDR3-1066) and 7(DDR3-1333)
• Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with tCCD = 4 which does not allow seamless read or
write [either On the fly using A12 or MRS]
• Bi-directional Differential Data Strobe
• On Die Termination using ODT pin
• Average Refresh Period 7.8us at lower then TCASE 85°C, 3.9us at 85°C < TCASE 95°C
• Asynchronous Reset
3. Address Configuration
Organization
1Gx4(4Gb) based Module
512Mx8(4Gb) based Module
2Gx4(8Gb DDP) based Module
Row Address
A0-A15
A0-A15
A0-A15
Column Address
A0-A9, A11
A0-A9
A0-A9, A11
Bank Address
BA0-BA2
BA0-BA2
BA0-BA2
Auto Precharge
A10/AP
A10/AP
A10/AP
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M393B2G73AH0 전자부품, 판매, 대치품
Registered DIMM
datasheet
Rev. 1.0
DDR3L SDRAM
7. Input/Output Functional Description
Symbol
CK0
CK0
CKE[1:0]
S[3:0]
ODT[1:0]
RAS, CAS, WE
VREFDQ
VREFCA
BA[2:0]
A[15:13,
12/BC,11,
10/AP,9:0]
DQ[63:0],
CB[7:0]
DM[8:0]
DQS[17:0]
DQS[17:0]
TDQS[17:9],
TDQS[17:9]
SA[2:0]
SDA
SCL
EVENT
VDDSPD
RESET
Par_In
Err_Out
TEST
Type
Input
Input
Input
Input
Input
Input
Supply
Supply
Input
Input
I/O
I/O
I/O
OUT
IN
I/O
IN
OUT
(open
drain)
Supply
IN
IN
OUT
(open
drain)
Polarity
Positive
Edge
Function
Positive line of the differential pair of system clock inputs that drives input to the on-DIMM Clock Driver.
Negative
Edge
Negative line of the differential pair of system clock inputs that drives the input to the on-DIMM Clock Driver.
CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers
Active High and output drivers of the SDRAMs. Taking CKE LOW provides PRECHARGE POWER-DOWN
and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank)
Enables the associated SDRAM command decoder when low and disables decoder when high.
When decoder is disabled, new commands are ignored and previous operations continue.
Active Low
These input signals also disable all outputs (except CKE and ODT) of the register(s) on the DIMM when both
inputs are high. When both S[1:0] are high, all register outputs (except CKE, ODT and Chip select) remain in
the previous state. For modules supporting 4 ranks, S[3:2] operate similarly to S[1:0] for a second set of reg-
ister outputs.
Active High On-Die Termination control signals
Active Low
When sampled at the positive
cuted by the SDRAM.
rising edge of
the
clock,
CAS, RAS,
and
WE define the
operation
to be
exe-
Reference voltage for DQ0-DQ63 and CB0-CB7
Reference voltage for A0-A15, BA0-BA2, RAS, CAS, WE, S0, S1, CKE0, CKE1, Par_In, ODT0 and ODT1.
Selects which SDRAM bank of eight is activated.
BA0 - BA2 define to which bank an Active, Read, Write or Precharge command is being applied. Bank
address also determines mode register is to be accessed during an MRS cycle.
Provided the row address for Active commands and the column address and Auto Precharge bit for Read/
Write commands to select one location out of the memory array in the respective bank. A10 is sampled dur-
ing a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks
(A10 HIGH). If only one bank is to be precharged, the bank is selected by BA. A12 is also utilized for BL 4/8
identification for "BL on the fly" during CAS command. The address inputs also provide the op-code during
Mode Register Set commands.
Data and Check Bit Input/Output pins
Active High Masks write data when high, issued concurrently with input data.
VDD, VSS Supply Power and ground for the DDR SDRAM input buffers and core logic.
VTT Supply Termination Voltage for Address/Command/Control/Clock nets.
Positive Edge Positive line of the differential data strobe for input and output data.
Negative Edge Negative line of the differential data strobe for input and output data.
TDQS/TDQS is applicable for X8 DRAMs only. When enabled via Mode Register A11=1 in MR1, DRAM will
enable the same termination resistance function on TDQS/TDQS that is applied to DQS/DQS. When dis-
abled via mode register A11=0 in MR1, DM/TDQS will provide the data mask function and TDQS is not used.
X4/X16 DRAMs must disable the TDQS function via mode register A11=0 in MR1
These signals are tied at the system planar to either VSS or VDDSPD to configure the serial SPD EEPROM
address range.
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be
connected from the SDA bus line to VDDSPD on the system planar to act as a pull-up.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected
from the SCL bus time to VDDSPD on the system planar to act as a pull-up.
Active Low
This signal indicates that a thermal event has been detected in the thermal sensing device.The system
should guarantee the electrical level requirement is met for the EVENT pin on TS/SPD part.
Serial EEPROM positive power supply wired to a separate power pin at the connector which supports from
3.0 Volt to 3.6 Volt (nominal 3.3V) operation.
The RESET pin is connected to the RESET pin on the register and to the RESET pin on the DRAM. When
low, all register outputs will be driven low and the Clock Driver clocks to the DRAMs and register(s) will be set
to low level (the Clock Driver will remain synchronized with the input clock)
Parity bit for the Address and Control bus. ("1 " : Odd, "0 ": Even)
Parity error detected on the Address and Control bus. A resistor may be connected from Err_Out
bus line to VDD on the system planar to act as a pull up.
Used by memory bus analysis tools (unused (NC) on memory DIMMs)
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M393B2G73AH0

240pin Registered DIMM

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