PDF M392B2G70BM0 Data sheet ( Hoja de datos )

Número de pieza	M392B2G70BM0
Descripción	240pin VLP Registered DIMM
Fabricantes	Samsung
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No Preview Available ! Rev. 1.2, Aug. 2011 M392B1G70BH0 M392B1G73BH0 M392B2G70BM0 M392B2G73BM0 M392B4G70BE0 240pin VLP Registered DIMM based on 4Gb B-die 78FBGA with Lead-Free & Halogen-Free (RoHS compliant) datasheet SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE. Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind. This document and all information discussed herein remain the sole and exclusive property of Samsung Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or other- wise. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. For updates or additional information about Samsung products, contact your nearest Samsung office. All brand names, trademarks and registered trademarks belong to their respective owners. ⓒ 2011 Samsung Electronics Co., Ltd. All rights reserved. -1- 1 page VLP Registered DIMM datasheet Rev. 1.2 DDR3 SDRAM 1. DDR3 VLP Registered DIMM Ordering Information Part Number2 Density Organization Component Composition M392B1G70BH0-CF8/H9/K0/MA M392B1G73BH0-CF8/H9/K0/MA M392B2G70BM0-CF8/H9/K0/MA M392B2G73BM0-CF8/H9 M392B4G70BE0-CF8/H9 8GB 8GB 16GB 16GB 32GB 1Gx72 1Gx72 2Gx72 2Gx72 4Gx72 1Gx4(K4B4G0446B-HC##)18 512Mx8(K4B4G0846B-HC##)18 DDP 2Gx4(K4B8G0446B-MC##)18 DDP 1Gx8(K4B8G0846B-MC##)18 QDP 4Gx4(K4BAG0446B-EC##)18 NOTE : 1. "##" - F8/H9/K0/MA 2. F8 - 1066Mbps 7-7-7 / H9 - 1333Mbps 9-9-9 / K0 - 1600Mbps 11-11-11 / MA - 1866Mbps 13-13-13 - DDR3-1866(13-13-13) is backward compatible to DDR3-1600(11-11-11), DDR3-1333(9-9-9), DDR3-1066(7-7-7) - DDR3-1600(11-11-11) is backward compatible to DDR3-1333(9-9-9), DDR3-1066(7-7-7) - DDR3-1333(9-9-9) is backward compatible to DDR3-1066(7-7-7) Number of Rank 1 2 2 4 4 Height 18.75mm 18.75mm 18.75mm 18.75mm 18.75mm 2. Key Features Speed tCK(min) CAS Latency tRCD(min) tRP(min) tRAS(min) tRC(min) DDR3-800 6-6-6 2.5 6 15 15 37.5 52.5 DDR3-1066 7-7-7 1.875 7 13.125 13.125 37.5 50.625 DDR3-1333 9-9-9 1.5 9 13.5 13.5 36 49.5 DDR3-1600 11-11-11 1.25 11 13.75 13.75 35 48.75 DDR3-1866 13-13-13 1.07 13 13.91 13.91 34 47.91 Unit ns nCK ns ns ns ns • JEDEC standard 1.5V ± 0.075V Power Supply • VDDQ = 1.5V ± 0.075V • 400MHz fCK for 800Mb/sec/pin, 533MHz fCK for 1066Mb/sec/pin, 667MHz fCK for 1333Mb/sec/pin, 800MHz fCK for 1600Mb/sec/pin, 933MHz fCK for 1866Mb/sec/pin • 8 independent internal bank • Programmable CAS Latency: 6,7,8,9,10,11,13 • Programmable Additive Latency(Posted CAS) : 0, CL - 2, or CL - 1 clock • Programmable CAS Write Latency(CWL) = 5 (DDR3-800), 6 (DDR3-1066), 7 (DDR3-1333), 8 (DDR3-1600) and 9 (DDR3-1866) • Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with tCCD = 4 which does not allow seamless read or write [either On the fly using A12 or MRS] • Bi-directional Differential Data Strobe • On Die Termination using ODT pin • Average Refresh Period 7.8us at lower then TCASE 85°C, 3.9us at 85°C < TCASE ≤ 95°C • Asynchronous Reset 3. Address Configuration Organization 1Gx4(4Gb) based Module 512Mx8(4Gb) based Module 2Gx4(8Gb DDP) based Module 1Gx8(8Gb DDP) based Module 4Gx4(16Gb QDP) based Module Row Address A0-A15 A0-A15 A0-A15 A0-A15 A0-A15 Column Address A0-A9, A11 A0-A9 A0-A9, A11 A0-A9 A0-A9, A11 Bank Address BA0-BA2 BA0-BA2 BA0-BA2 BA0-BA2 BA0-BA2 Auto Precharge A10/AP A10/AP A10/AP A10/AP A10/AP -5- 5 Page VLP Registered DIMM datasheet 10. Function Block Diagram: 10.1 8GB, 1Gx72 Module (Populated as 1 rank of x4 DDR3 SDRAMs) Rev. 1.2 DDR3 SDRAM DQS8 DQS8 VSS CB[3:0] DQS DQS DM DQ[3:0] D8 ZQ DQS17 DQS17 VSS CB[7:4] DQS ZQ DQS8 DQS DQS8 DM DQ[3:0] D17 VSS DQ[35:32] DQS ZQ DQS17 DQS DQS17 DM DQ[3:0] D4 VSS DQ[39:36] DQS DQS DM DQ[3:0] D13 ZQ DQS3 DQS3 VSS DQ[27:24] DQS ZQ DQS17 DQS DQS17 DM DQ[3:0] D3 VSS DQ[31:28] DQS ZQ DQS8 DQS DQS8 DM DQ[3:0] D12 VSS DQ[43:40] DQS ZQ DQS17 DQS DQS17 DM DQ[3:0] D5 VSS DQ[47:44] DQS DQS DM DQ[3:0] D14 ZQ DQS8 DQS8 VSS DQ[19:16] DQS ZQ DQS17 DQS DQS17 DM DQ[3:0] D2 VSS DQ[23:20] DQS ZQ DQS8 DQS DQS8 DM DQ[3:0] D11 VSS DQ[51:48] DQS ZQ DQS17 DQS DQS17 DM DQ[3:0] D6 VSS DQ[55:52] DQS DQS DM DQ[3:0] D15 ZQ DQS8 DQS8 VSS DQ[11:8] DQS ZQ DQS17 DQS DQS17 DM DQ[3:0] D1 VSS DQ[15:12] DQS ZQ DQS8 DQS DQS8 DM DQ[3:0] D10 VSS DQ[59:56] DQS ZQ DQS17 DQS DQS17 DM DQ[3:0] D7 VSS DQ[63:60] DQS DQS DM DQ[3:0] D16 ZQ DQS8 DQS8 VSS DQ[3:0] DQS DQS DM DQ[3:0] D0 ZQ DQS17 DQS17 VSS DQ[7:4] DQS DQS DM DQ[3:0] D9 ZQ Vtt SCL EVENT Thermal sensor with SPD EVENT A0 A1 A2 VDDSPD SDA VDD VTT Serial PD D0 - D17 SA0 SA1 SA2 VREFCA D0 - D17 VREFDQ D0 - D17 VSS D0 - D17 NOTE : 1. Unless otherwise noted, resistor values are 15Ω ± 5%. 2. See the wiring diagrams for all resistors associated with the command, address and control bus. 3. ZQ resistors are 240Ω ± 1% . For all other resistor values refer to the appropriate wiring diagram. Vtt S0 S1* RS0A-> CS0 : SDRAMs D[3:0], D[12:8], D17 RS0B-> CS0 : SDRAMs D[7:4], D[16:13]] BA[N:0] A[N:0] RAS CAS WE CKE0 ODT0 RBA[N:0]A -> BA[N:0] : SDRAMs D[3:0], D[12:8], D17 RBA[N:0]B -> BA[N:0] : SDRAMs D[7:4], D[16:13] RA[N:0]A -> A[N:0] : SDRAMs D[3:0], D[12:8], D17 RA[N:0]B -> A[N:0] : SDRAMs D[7:4], D[16:13] RRASA -> RAS : SDRAMs D[3:0], D[12:8], D17 RRASB -> RAS : SDRAMs D[7:4], D[16:13] RCASA -> CAS : SDRAMs D[3:0], D[12:8], D17 1:2 RCASB -> CAS : SDRAMs D[7:4], D[16:13] R RWEA -> WE : SDRAMs D[3:0], D[12:8], D17 E RWEB -> WE : SDRAMs D[7:4], D[16:13] G RCKE0A -> CKE0 : SDRAMs D[3:0], D[12:8], D17 I RCKE0B -> CKE0 : SDRAMs D[7:4], D[16:13] S T RODT0A -> ODT0 : SDRAMs D[3:0], D[12:8], D17 E RODT0B -> ODT0 : SDRAMs D[7:4], D[16:13] R CK0 CK0 PCK0A -> CK : SDRAMs D[3:0], D[12:8], D17 PCK0B -> CK : SDRAMs D[7:4], D[16:13] PCK0A -> CK : SDRAMs D[3:0], D[12:8], D17 PCK0B -> CK : SDRAMs D[7:4], D[16:13] PAR_IN RESET QERR RST Err_out RST : SDRAMs D[17:0] *S[3:2], CKE1, ODT1, CK1 and CK1 are NC (Unused register inputs ODT1 and CKE1 have a 330 Ω resistor to ground) - 11 - 11 Page

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