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PDF L170E3-5 Data sheet ( Hoja de datos )
| Número de pieza | L170E3-5 | |
| Descripción | SXGA Color TFT-LCD Module | |
| Fabricantes | AUO | |
| Logotipo |  |
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Product Specifications
17.0” SXGA Color TFT-LCD Module
Model Name: L170E3
EC: -5
() Preliminary Specifications
( ) Final Specifications
Note: This Specification is subject to change without notice.
(C) Copyright AU Optronics, Inc.
January, 2001 All Rights Reserved.
No Reproduction and Redistribution Allowed.
L170E3-5 Ver0.2
1/24
1 page  
2.2 Functional Block Diagram
The following diagram shows the functional block of the 17.0 inches Color TFT-LCD Module:
LVDS
+5V
ASIC(Leo 3)
LVDS
Receiver
Timing
Controller
DC/DC
Converter
Gamma
Correction
Y PCB
G1
TFT-LCD
1280*(3)*1024
Pixels
G1024
D1
X-Driver IC
D3840
4 CCFL
I/F + X PCB
DC POWER
Inverter
JAE FI-X30S-HF
Mating Type JAE FI-X30S-H
JST BHR-04VS-1
Mating Type SM04(4.0)B-BHS-1-TB
(C) Copyright AU Optronics, Inc.
January, 2001 All Rights Reserved.
No Reproduction and Redistribution Allowed.
L170E3-5 Ver0.2
5/24
5 Page 
3.4 Signal Description
The module using a pair of LVDS receiver SN75LVDS82(Texas Instruments) or compatible. LVDS is a
differential signal technology for LCD interface and high speed data transfer device. Transmitter shall be
SN75LVDS83(negative edge sampling) or compatible. The first LVDS port(RxOxxx) transmits odd pixels
while the second LVDS port(RxExxx) transmits even pixels.
PIN # SIGNAL NAME
DESCRIPTION
1 RxO0-
Negative LVDS differential data input (Odd data)
2 RxO0+
Positive LVDS differential data input (Odd data)
3 RxO1-
Negative LVDS differential data input (Odd data)
4 RxO1+
5 RxO2-
6 RxO2+
7 GND
8 RxOC-
9 RxOC+
10 RxO3-
11 RxO3+
12 RxE0-
13 RxE0+
14 GND
15 RxE1-
16 RxE1+
17 GND
18 RxE2-
19 RxE2+
20 RxEC-
21 RxEC+
22 RxE3-
23 RxE3+
24 GND
25 NC
26 NC
27 NC
28 POWER
29 POWER
30 POWER
Positive LVDS differential data input (Odd data)
Negative LVDS differential data input (Odd data, H-Sync,V-Sync,DSPTMG)
Positive LVDS differential data input (Odd data, H-Sync,V-Sync,DSPTMG)
Power Ground
Negative LVDS differential clock input (Odd clock)
Positive LVDS differential clock input (Odd clock)
Negative LVDS differential data input (Odd data)
Positive LVDS differential data input (Odd data)
Negative LVDS differential data input (Even clock)
Positive LVDS differential data input (Even data)
Power Ground
Positive LVDS differential data input (Even data)
Negative LVDS differential data input (Even data)
Power Ground
Negative LVDS differential data input (Even data)
Positive LVDS differential data input (Even data)
Negative LVDS differential clock input (Even clock)
Positive LVDS differential clock input (Even clock)
Negative LVDS differential data input (Even data)
Positive LVDS differential data input (Even data)
Power Ground
-
-
-
Power
Power
Power
Note: Input signals of odd and even clock shall be the same timing.
LVDS DATA Name
Description
DSP
Display Timing :When the signal is high, the pixel data shall be valid to be displayed
V-S Vertical Sync :Both Positive and Negative polarity are acceptable
H-S Horizontal Sync :Both Positive and Negative polarity are acceptable
(C) Copyright AU Optronics, Inc.
January, 2001 All Rights Reserved.
No Reproduction and Redistribution Allowed.
L170E3-5 Ver0.2
11/24
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet L170E3-5.PDF ] | |
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