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N25Q128A 데이터시트 PDF




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부품번호 N25Q128A 기능
기능 NOR Flash Memory
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N25Q128A 데이터시트, 핀배열, 회로
128Mb, Multiple I/O Serial Flash Memory
Features
Micron Serial NOR Flash Memory
1.8V, Multiple I/O, 4KB Sector Erase
N25Q128A
Features
• SPI-compatible serial bus interface
• 108 MHz (MAX) clock frequency
• 1.7–2.0V single supply voltage
• Dual/quad I/O instruction provides increased
throughput up to 432 MHz
• Supported protocols
– Extended SPI, dual I/O, and quad I/O
• Execute-in-place (XIP) mode for all three protocols
– Configurable via volatile or nonvolatile registers
– Enables memory to work in XIP mode directly af-
ter power-on
• PROGRAM/ERASE SUSPEND operations
• Continuous read of entire memory via a single com-
mand
– Fast read
– Quad or dual output fast read
– Quad or dual I/O fast read
• Flexible to fit application
– Configurable number of dummy cycles
– Output buffer configurable
• Software reset
• 64-byte, user-lockable, one-time programmable
(OTP) dedicated area
• Erase capability
– Subsector erase 4KB uniform granularity blocks
– Sector erase 64KB uniform granularity blocks
– Full-chip erase
• Write protection
– Software write protection applicable to every
64KB sector via volatile lock bit
– Hardware write protection: protected area size
defined by five nonvolatile bits (BP0, BP1, BP2,
BP3, and TB)
– Additional smart protections, available upon re-
quest
• Electronic signature
– JEDEC-standard 2-byte signature (BB18h)
– Unique ID code (UID): 17 read-only bytes, in-
cluding:
• Two additional extended device ID (EDID)
bytes to identify device factory options
• Customized factory data (14 bytes)
• Minimum 100,000 ERASE cycles per sector
• More than 20 years data retention
• Packages JEDEC standard, all RoHS compliant
– F7 = V-PDFN-8 6mm x 5mm Sawn (MLP8 6mm x
5mm)
– F8 = V-PDFN-8 8mm x 6mm (MLP8 8mm x 6mm)
– 12 = T-PBGA-24b05 6mm x 8mm
– SF = SOP2-16 300 mils body width (SO16W)
– SE = SOP2-8 208 mils body width (SO8W)
PDF: 09005aef845665f6
n25q_128mb_1_8v_65nm.pdf - Rev. P 05/14 EN
1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.




N25Q128A pdf, 반도체, 판매, 대치품
128Mb, Multiple I/O Serial Flash Memory
Features
List of Figures
Figure 1: Logic Diagram ................................................................................................................................... 7
Figure 2: 8-Pin, VDFPN8 – MLP8 and SOP2 – SO8W (Top View) ......................................................................... 8
Figure 3: 16-Pin, Plastic Small Outline – SO16 (Top View) .................................................................................. 8
Figure 4: 24-Ball TBGA (Balls Down) ................................................................................................................ 9
Figure 5: Block Diagram ................................................................................................................................ 12
Figure 6: Bus Master and Memory Devices on the SPI Bus ............................................................................... 18
Figure 7: SPI Modes ....................................................................................................................................... 18
Figure 8: Internal Configuration Register ........................................................................................................ 20
Figure 9: READ REGISTER Command ............................................................................................................ 30
Figure 10: WRITE REGISTER Command ......................................................................................................... 32
Figure 11: READ LOCK REGISTER Command ................................................................................................. 34
Figure 12: WRITE LOCK REGISTER Command ............................................................................................... 35
Figure 13: READ ID and MULTIPLE I/O Read ID Commands .......................................................................... 37
Figure 14: READ Command ........................................................................................................................... 41
Figure 15: FAST READ Command ................................................................................................................... 41
Figure 16: DUAL OUTPUT FAST READ ........................................................................................................... 42
Figure 17: DUAL INPUT/OUTPUT FAST READ Command .............................................................................. 42
Figure 18: QUAD OUTPUT FAST READ Command ......................................................................................... 43
Figure 19: QUAD INPUT/OUTPUT FAST READ Command ............................................................................. 43
Figure 20: PAGE PROGRAM Command .......................................................................................................... 45
Figure 21: DUAL INPUT FAST PROGRAM Command ...................................................................................... 46
Figure 22: EXTENDED DUAL INPUT FAST PROGRAM Command ................................................................... 46
Figure 23: QUAD INPUT FAST PROGRAM Command ..................................................................................... 47
Figure 24: EXTENDED QUAD INPUT FAST PROGRAM Command ................................................................... 48
Figure 25: WRITE ENABLE and WRITE DISABLE Command Sequence ............................................................ 50
Figure 26: SUBSECTOR and SECTOR ERASE Command .................................................................................. 52
Figure 27: BULK ERASE Command ................................................................................................................ 53
Figure 28: RESET ENABLE and RESET MEMORY Command ........................................................................... 56
Figure 29: READ OTP Command .................................................................................................................... 57
Figure 30: PROGRAM OTP Command ............................................................................................................ 59
Figure 31: XIP Mode Directly After Power-On .................................................................................................. 61
Figure 32: Power-Up Timing .......................................................................................................................... 63
Figure 33: Reset AC Timing During PROGRAM or ERASE Cycle ........................................................................ 66
Figure 34: Reset Enable ................................................................................................................................. 66
Figure 35: Serial Input Timing ........................................................................................................................ 66
Figure 36: Write Protect Setup and Hold During WRITE STATUS REGISTER Operation (SRWD = 1) ................... 67
Figure 37: Hold Timing .................................................................................................................................. 68
Figure 38: Output Timing .............................................................................................................................. 68
Figure 39: VPPH Timing .................................................................................................................................. 69
Figure 40: AC Timing Input/Output Reference Levels ...................................................................................... 71
Figure 41: V-PDFN-8 6mm x 5mm Sawn (MLP8) – Package Code: F7 ................................................................ 75
Figure 42: V-PDFN-8 8mm x 6mm (MLP8) – Package Code: F8 ........................................................................ 76
Figure 43: T-PBGA-24b05 6mm x 8mm – Package Code: 12 .............................................................................. 77
Figure 44: SOP2-16 (300 mils body width) – Package Code: SF ......................................................................... 78
Figure 45: SOP2-8 (208 mils body width) – Package Code: SE ........................................................................... 79
PDF: 09005aef845665f6
n25q_128mb_1_8v_65nm.pdf - Rev. P 05/14 EN
4 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.

4페이지










N25Q128A 전자부품, 판매, 대치품
128Mb, Multiple I/O Serial Flash Memory
Device Description
Device Configurability
The N25Q family offers additional features that are configured through the nonvolatile
configuration register for default and/or nonvolatile settings. Volatile settings can be
configured through the volatile and volatile-enhanced configuration registers. These
configurable features include the following:
• Number of dummy cycles for the fast READ commands
• Output buffer impedance
• SPI protocol types (extended SPI, DIO-SPI, or QIO-SPI)
• Required XIP mode
• Enabling/disabling HOLD (RESET function)
• Enabling/disabling wrap mode
Figure 1: Logic Diagram
VCC
DQ0
C
S#
VPP/W#/DQ2
HOLD#/DQ3
DQ1
VSS
Note: 1. Reset functionality is available in devices with a dedicated part number. See Part Num-
ber Ordering Information for more details.
PDF: 09005aef845665f6
n25q_128mb_1_8v_65nm.pdf - Rev. P 05/14 EN
7 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.

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관련 데이터시트

부품번호상세설명 및 기능제조사
N25Q128

serial flash memory

Numonyx B.V
Numonyx B.V
N25Q128A

NOR Flash Memory

Micron
Micron

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