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PDF Si8422 Data sheet ( Hoja de datos )
| Número de pieza | Si8422 | |
| Descripción | SINGLE AND DUAL-CHANNEL DIGITAL ISOLATORS | |
| Fabricantes | Silicon Laboratories | |
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Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
LOW-POWER, SINGLE AND DUAL-CHANNEL
DIGITAL ISOLATORS
Features
High-speed operation
DC to 150 Mbps
No start-up initialization required
Wide Operating Supply Voltage:
2.6–5.5 V
Up to 5000 VRMS isolation
High electromagnetic immunity
Ultra low power (typical)
5 V Operation:
< 2.6 mA/channel at 1 Mbps
< 6.8 mA/channel at 100 Mbps
2.70 V Operation:
< 2.3 mA/channel at 1 Mbps
< 4.6 mA/channel at 100 Mbps
Schmitt trigger inputs
Selectable fail-safe mode
Default high or low output
Precise timing (typical)
11 ns propagation delay max
1.5 ns pulse width distortion
0.5 ns channel-channel skew
2 ns propagation delay skew
5 ns minimum pulse width
Transient immunity 45 kV/µs
AEC-Q100 qualification
Wide temperature range
–40 to 125 °C at 150 Mbps
RoHS compliant packages
SOIC-16 wide body
SOIC-8 narrow body
Applications
Industrial automation systems
Medical electronics
Hybrid electric vehicles
Isolated switch mode supplies
Isolated ADC, DAC
Motor control
Power inverters
Communication systems
Safety Regulatory Approvals
UL 1577 recognized
VDE certification conformity
Up to 5000 VRMS for 1 minute
CSA component notice 5A approval
IEC 60950-1, 61010-1, 60601-1
IEC 60747-5-5
(VDE0884 Part 5)
EN60950-1 (reinforced insulation)
(reinforced insulation)
Description
Silicon Lab's family of ultra-low-power digital isolators are CMOS devices offering
substantial data rate, propagation delay, power, size, reliability, and external BOM
advantages when compared to legacy isolation technologies. The operating
parameters of these products remain stable across wide temperature ranges and
throughout device service life for ease of design and highly uniform performance.
All device versions have Schmitt trigger inputs for high noise immunity and only
require VDD bypass capacitors.
Data rates up to 150 Mbps are supported, and all devices achieve worst-case
propagation delays of less than 10 ns. Ordering options include a choice of
isolation ratings (up to 5 kV) and a selectable fail-safe operating mode to control
the default output state during power loss. All products are safety certified by UL,
CSA, and VDE, and products in wide-body packages support reinforced insulation
withstanding up to 5 kVRMS.
Ordering Information:
See page 29.
Rev. 1.3 3/14
Copyright © 2014 by Silicon Laboratories
Si8410/20/21 / Si8422/23
1 page  
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
Table 1. Electrical Characteristics (Continued)
(VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = –40 to 125 ºC)
Parameter
Symbol Test Condition
Min
Typ Max Unit
1 Mbps Supply Current (All inputs = 500 kHz square wave, CL = 15 pF on all outputs)
Si8410Ax, Bx
VDD1
VDD2
— 2.0 3.0 mA
— 1.1 1.7
Si8420Ax, Bx
VDD1
VDD2
— 3.5 5.3 mA
— 1.9 2.9
Si8421Ax, Bx
VDD1
VDD2
— 2.8 4.2 mA
— 2.8 4.2
Si8422Ax, Bx
VDD1
VDD2
— 2.8 4.2 mA
— 2.8 4.2
Si8423Ax, Bx
VDD1
VDD2
— 3.4 5.1
— 1.9 2.9
10 Mbps Supply Current (All inputs = 5 MHz square wave, CL = 15 pF on all outputs)
mA
Si8410Bx
VDD1
VDD2
— 2.1 3.1 mA
— 1.5 2.1
Si8420Bx
VDD1
VDD2
Si8421Bx
— 3.6 5.4 mA
— 2.6 3.6
VDD1
VDD2
— 3.2 4.5 mA
— 3.2 4.5
Si8422Bx
VDD1
VDD2
Si8423Bx
— 3.2 4.5 mA
— 3.2 4.5
VDD1
VDD2
—
—
3.4
2.5
5.1
3.5
mA
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.3
5
5 Page 
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
Table 2. Electrical Characteristics (Continued)
(VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA = –40 to 125 °C)
Parameter
Symbol Test Condition
Min
Typ Max Unit
All Models
Output Rise Time
tr CL = 15 pF — 2.0 4.0 ns
Output Fall Time
tf CL = 15 pF — 2.0 4.0 ns
Peak Eye Diagram Jitter
tJIT(PK)
See Figure 6
—
350 — ps
Common Mode Transient
Immunity
Start-up Time3
CMTI
tSU
VI = VDD or 0 V
20
—
45 — kV/µs
15 40 µs
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.3
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet Si8422.PDF ] | |
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