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부품번호 | SI8663 기능 |
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기능 | LOW POWER SIX-CHANNEL DIGITAL ISOLATOR | ||
제조업체 | Silicon Laboratories | ||
로고 | |||
전체 30 페이지수
Si8660/61/62/63
LOW POWER SIX-CHANNEL DIGITAL ISOLATOR
Features
High-speed operation
Selectable fail-safe mode
DC to 150 Mbps
Default high or low output
No start-up initialization required
(ordering option)
Wide Operating Supply Voltage Precise timing (typical)
2.5–5.5 V
10 ns propagation delay
Up to 5000 VRMS isolation
1.5 ns pulse width distortion
60-year life at rated working voltage 0.5 ns channel-channel skew
High electromagnetic immunity
2 ns propagation delay skew
Ultra low power (typical)
5 V Operation
1.6 mA per channel at 1 Mbps
5.5 mA per channel at 100 Mbps
2.5 V Operation
1.5 mA per channel at 1 Mbps
5 ns minimum pulse width
Transient Immunity 50 kV/µs
AEC-Q100 qualification
Wide temperature range
–40 to 125 °C
RoHS-compliant packages
3.5 mA per channel at 100 Mbps
SOIC-16 wide body
Schmitt trigger inputs
SOIC-16 narrow body
Applications
Industrial automation systems
Medical electronics
Hybrid electric vehicles
Isolated switch mode supplies
Isolated ADC, DAC
Motor control
Power inverters
Communication systems
Ordering Information:
See page 30.
Safety Regulatory Approvals
UL 1577 recognized
VDE certification conformity
Up to 5000 VRMS for 1 minute
IEC 60747-5-2
CSA component notice 5A approval
(VDE0884 Part 2)
IEC 60950-1, 61010-1, 60601-1
EN60950-1
(reinforced insulation)
(reinforced insulation)
CQC certification approval
GB4943.1
Description
Silicon Lab's family of ultra-low-power digital isolators are CMOS devices
offering substantial data rate, propagation delay, power, size, reliability, and
external BOM advantages over legacy isolation technologies. The operating
parameters of these products remain stable across wide temperature ranges
and throughout device service life for ease of design and highly uniform
performance. All device versions have Schmitt trigger inputs for high noise
immunity and only require VDD bypass capacitors.
Data rates up to 150 Mbps are supported, and all devices achieve propagation
delays of less than 10 ns. Ordering options include a choice of isolation ratings
(2.5, 3.75 and 5 kV) and a selectable fail-safe operating mode to control the
default output state during power loss. All products >1 kVRMS are safety
certified by UL, CSA, VDE, and CQC, and products in wide-body packages
support reinforced insulation withstanding up to 5 kVRMS.
Rev. 1.5 9/13
Copyright © 2013 by Silicon Laboratories
Si8660/61/62/63
Si8660/61/62/63
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Ambient Operating Temperature*
TA –40 25 125 °C
Supply Voltage
VDD1
2.5
—
5.5 V
VDD2
2.5
—
5.5 V
*Note: The maximum ambient temperature is dependent on data frequency, output loading, number of operating channels,
and supply voltage.
Table 2. Electrical Characteristics
(VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = –40 to 125 °C)
Parameter
Symbol
Test Condition
Min Typ Max Unit
VDD Undervoltage
Threshold
VDDUV+
VDD1, VDD2 rising
1.95 2.24 2.375 V
VDD Undervoltage
Threshold
VDDUV–
VDD1, VDD2 falling
1.88 2.16 2.325 V
VDD Undervoltage
Hysteresis
VDDHYS
50 70 95 mV
Positive-Going Input
Threshold
VT+
All inputs rising
1.4 1.67 1.9 V
Negative-Going
Input Threshold
VT– All inputs falling
1.0 1.23 1.4 V
Input Hysteresis
High Level Input Voltage
Low Level Input Voltage
High Level Output Volt-
age
VHYS
VIH
VIL
VOH
loh = –4 mA
0.38
2.0
—
VDD1,VDD2 – 0.4
0.44
—
—
4.8
0.50 V
—V
0.8 V
—V
Low Level Output Volt-
age
VOL
lol = 4 mA
— 0.2 0.4 V
Input Leakage Current
Output Impedance1
IL
ZO
— — ±10 µA
— 50 —
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
4 Rev. 1.5
4페이지 Si8660/61/62/63
Table 2. Electrical Characteristics (Continued)
(VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = –40 to 125 °C)
Parameter
Symbol
Test Condition
Min Typ Max Unit
Timing Characteristics
Si866xBx, Ex
Maximum Data Rate
0 — 150 Mbps
Minimum Pulse Width
— — 5.0 ns
Propagation Delay
Pulse Width Distortion
|tPLH - tPHL|
Propagation Delay
Skew2
Channel-Channel Skew
All Models
Output Rise Time
tPHL, tPLH
PWD
tPSK(P-P)
tPSK
tr
See Figure 1
See Figure 1
CL = 15 pF
(See Figure 1)
5.0 8.0 13 ns
— 0.2 4.5 ns
— 2.0 4.5 ns
— 0.4 2.5 ns
— 2.5 4.0 ns
Output Fall Time
tf CL = 15 pF
(See Figure 1)
— 2.5 4.0 ns
Peak Eye Diagram Jitter tJIT(PK)
See Figure 7
— 350 — ps
Common Mode
Transient Immunity
CMTI
VI = VDD or 0 V
VCM = 1500 V
(See Figure 2)
35 50 — kV/µs
Startup Time3
tSU
— 15 40 µs
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
1.4 V
Typical
Input
1.4 V
Typical
Output
tPLH
tPHL
90%
10%
90%
10%
tr tf
Figure 1. Propagation Delay Timing
Rev. 1.5
7
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DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |