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PDF D720133 Data sheet ( Hoja de datos )
| Número de pieza | D720133 | |
| Descripción | UPD720133 | |
| Fabricantes | NEC | |
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PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
µPD720133
USB2.0 to IDE Bridge
The µPD720133 is designed to function as a bridge between USB 2.0 and ATA/ATAPI. The µPD720133 complies
with the Universal Serial Bus Specification Revision 2.0 full-/high-speed signaling and works up to 480 Mbps. The
µPD720133 consists of a CISC processor, an ATA/ATAPI controller, an endpoint controller (EPC), a serial interface
engine (SIE), and an USB2.0 transceiver. The USB2.0 protocol and class specific protocols (bulk only protocol) are
handled by the USB2.0 transceiver, the SIE and the EPC. The V30MZ CISC processor in the µPD720133 takes care of
the activities in the transport layer. The firmware controlling the µPD720133 is located in an embedded ROM.
FEATURES
• Compliant with Universal Serial Bus Specification Revision 2.0 (Data Rate 12/480 Mbps)
• Compliant with ATA/ATAPI-6 (LBA48, PIO Mode 0-4, Multi Word DMA Mode 0-2, Ultra DMA Mode 0-4)
• USB2.0 high-speed bus powered device capability
• Certified by USB implementers forum and granted with USB 2.0 high-speed Logo (TID: 40001985)
• One USB2.0 high-speed transceiver / receiver with full-speed transceiver / receiver
• USB2.0 High-speed or Full-speed packet protocol sequencer (Serial Interface Engine)
• Automatic chirp assertion and full-/high-speed mode change
• USB Reset, Suspend and Resume signaling detection
• Supports power control functionality for IDE device as CD-ROM and HDD
• Supports set feature (TEST_MODE) functionality
• System Clock is generated by 30 MHz X’tal
• 2.5 V and 3.3 V power supply
ORDERING INFORMATION
Part Number
µPD720133GB-YEU-A
µPD720133GB-YEU-Y
Package
64-pin plastic TQFP (fine pitch) (10 × 10) Lead-free product
64-pin plastic TQFP (fine pitch) (10 × 10) High heat-resistance product
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. S17100EJ2V0DS00 (2nd edition)
Date Published June 2004 NS CP (N)
Printed in Japan
The mark shows major revised points.
2004
1 page  
µPD720133
1. PIN INFORMATION
Pin Name
I/O
Buffer Type
Active Level
Function
XIN I
XOUT
O
RESETB
I
IDECS(1:0)B
O (I/O)
IDEA(2:0)
O (I/O)
IDEINT
I
IDEDAKB
O (I/O)
IDEIORDY
I
IDEIORB
O (I/O)
IDEIOWB
O (I/O)
IDEDRQ
I
IDED(15:0)
I/O
IDERSTB
O (I/O)
CMB_BSY (GPIO7)
I/O
CMB_STATE (GPIO6) I/O
DPC (GPIO5)
I/O
SDA (PIO0)
I/O
SCL (PIO1)
I/O
VBUS
I
DP I/O
DM I/O
RSDP
O
RSDM
O
RPU
A
RREF
A
SCAN
I
TEST
I
AVDD25
VDD25
VDD33
AVSS
VSS
2.5 V Input
2.5 V Output
3.3 V Schmitt Input
5 V tolerant Output
5 V tolerant Output
5 V tolerant Input
5 V tolerant Output
5 V tolerant Input
5 V tolerant Output
5 V tolerant Output
5 V tolerant Input
5 V tolerant I/O
5 V tolerant Output
3.3 V I/O
3.3 V I/O
3.3 V I/O
3.3 V I/O
3.3 V I/O
5 V Schmitt Input Note
USB high speed D+ I/O
USB high speed D− I/O
USB full speed D+ Output
USB full speed D− Output
USB Pull-up control
Analog
3.3 V Input
3.3 V Input
Low
Low
High
Low
High
Low
Low
High
Low
System clock input or oscillator In
Oscillator out
Asynchronous reset signaling
IDE host chip select
IDE address bus
IDE interrupt request from device to host
IDE DMA acknowledge
IDE IO channel ready
IDE IO read strobe
IDE IO write strobe
IDE DMA request from device to host
IDE data bus
IDE reset from host to device
Combo IDE bus busy
Combo IDE bus state
Power control signaling for IDE device
Serial ROM data signaling
Serial ROM clock signaling
VBUS monitoring
USB’s high speed D+ signal
USB’s high speed D− signal
USB’s full speed D+ signal
USB’s full speed D− signal
USB’s 1.5 kΩ pull-up resistor control
Reference resistor
Scan mode control
Test mode setting
2.5 V VDD for Analog circuit
2.5 V VDD
3.3 V VDD
VSS for Analog circuit
VSS
Note
VBUS pin may be used to monitor for VBUS line even if VDD33, VDD25, and AVDD25 are shut off. The System
Designer must ensure that the input voltage level for VBUS pin is less than 3.0 V. [that is the absolute
maximum rating].
Remarks 1. “5 V tolerant“ means that the buffer is a 3.3 V buffer with 5 V tolerant circuit.
2. The signal marked as “(I/O)” in the above table operates as I/O signals during testing. They should be
ignored under normal operation.
Preliminary Data Sheet S17100EJ2V0DS
5
5 Page 
µPD720133
2.5 Power Control
To realize bus-powered or high performance self-powered USB2.0 to IDE Bridge system, the µPD720133 has
two internal system clock mode. One is 7.5 MHz for bus-powered mode and another is 60 MHz for self-powered
mode. The µPD720133 controls the power state by events as follows. The word with under line indicates event.
The Italic word indicates the power state.
Figure 2-3. Power State Control
(a) Bus-powered Mode
Power OFF Power OFF
Vbus ON
Connect
Hardware Reset
Idle Mode
Power = PRESET
Bus Reset Default State
Vbus OFF
FS CONNECT
HS CONNECT
FS Enumeration
HS Enumeration
State
Power = PENUM_FS
Suspend
Set Configuration
Resume
State
Power = PENUM_HS
Resume
Set Configuration
Suspend
Configured Suspend
Suspend
Suspend
Configured
Suspend
State
Resume
Mode
State Resume
Mode
Suspend
Power = PSPND
Suspend
Power = PSPND
Resume
Resume
FS Operation
State
Power = PFS_B
HS Operation
State
Power = PHS_B
(b) Self-powered Mode
Power OFF
Power OFF
Power ON
Hardware Reset
Idle Mode
Power = PRESET
CMB_STATE = 1 CMB_STATE = 0
Bus Reset
IDE Bus
Release
State
Power = PCOMBO
FS CONNECT
Disconnect
Mode
Vbus OFF
Vbus ON
Connect
Default
State
HS CONNECT
FS Enumeration
State
Resume
Power = PENUM_FS
Set Configuration
Suspend
Suspend
Configured
State
Resume
Suspend
HS Enumeration
State
Power = PENUM_HS
Resume
Set Configuration
Suspend
Suspend
Mode
Power = PSPND
Configured
State
Suspend
Resume
Suspend
Suspend
Mode
Power = PSPND
FS Operation
State
Power = PFS_S
Resume
HS Operation
State
Power = PHS_S
Resume
Preliminary Data Sheet S17100EJ2V0DS
11
11 Page | ||
| Páginas | Total 40 Páginas | |
| PDF Descargar | [ Datasheet D720133.PDF ] | |
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