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UC2844 데이터시트 PDF




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부품번호 UC2844 기능
기능 (UC2844 / UC2845) High Performance Current Mode Controllers
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UC2844 데이터시트, 핀배열, 회로
UC3844, UC3845, UC2844,
UC2845
High Performance
Current Mode Controllers
The UC3844, UC3845 series are high performance fixed frequency
current mode controllers. They are specifically designed for OffLine
and DCtoDC converter applications offering the designer a cost
effective solution with minimal external components. These integrated
circuits feature an oscillator, a temperature compensated reference, high
gain error amplifier, current sensing comparator, and a high current
totem pole output ideally suited for driving a power MOSFET.
Also included are protective features consisting of input and
reference undervoltage lockouts each with hysteresis, cyclebycycle
current limiting, a latch for single pulse metering, and a flipflop which
blanks the output off every other oscillator cycle, allowing output dead
times to be programmed for 50% to 70%.
These devices are available in an 8pin dualinline plastic package
as well as the 14pin plastic surface mount (SOIC14). The SOIC14
package has separate power and ground pins for the totem pole output
stage.
The UCX844 has UVLO thresholds of 16 V (on) and 10 V (off),
ideally suited for offline converters. The UCX845 is tailored for
lower voltage applications having UVLO thresholds of 8.5 V (on) and
7.6 V (off).
Features
Current Mode Operation to 500 kHz Output Switching Frequency
Output Deadtime Adjustable from 50% to 70%
Automatic Feed Forward Compensation
Latching PWM for CycleByCycle Current Limiting
Internally Trimmed Reference with Undervoltage Lockout
High Current Totem Pole Output
Input Undervoltage Lockout with Hysteresis
Low Startup and Operating Current
Direct Interface with ON Semiconductor SENSEFETt Products
PbFree Packages are Available
VCC 7(12)
Vref
8(14)
RTCT
4(7)
Voltage
Feedback
2(3)
1(1)
Output
Comp.
R
5.0V
Reference
VCC
Undervoltage
Lockout
R
Vref
Undervoltage
Lockout
Oscillator
+
Error
Amplifier
Flip
Flop
&
Latching
PWM
GND 5(9)
Pin numbers in parenthesis are for the D suffix SOIC14 package.
Figure 1. Simplified Block Diagram
VC
7(11)
Output
6(10)
PWR GND
5(8)
Current
Sense
3(5)
© Semiconductor Components Industries, LLC, 2006
July, 2006 Rev. 7
1
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8
1
14
1
8
1
PDIP8
N SUFFIX
CASE 626
SOIC14
D SUFFIX
CASE 751A
SOIC8
D1 SUFFIX
CASE 751A
PIN CONNECTIONS
Compensation 1
Voltage Feedback 2
Current Sense 3
RT/CT 4
8 Vref
7 VCC
6 Output
5 GND
(Top View)
Compensation 1
NC 2
Voltage Feedback 3
NC 4
Current Sense 5
NC 6
RT/CT 7
14 Vref
13 NC
12 VCC
11 VC
10 Output
9 GND
8 Power Ground
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 14 of this data sheet.
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page page 14 of this data sheet.
Publication Order Number:
UC3844/D




UC2844 pdf, 반도체, 판매, 대치품
UC3844, UC3845, UC2844, UC2845
10 75
0 VCC = 15 V
50 TA = 25°C
70
1.0 nF
2.0 nF
20
5.0 nF
65
10 CT = 10 nF
5.0 60
2.0 NOTE: Output switches
at one−half the oscillator
frequency.
1.0
10 k 20 k
50 k
100 k 200 k
500 k
fosc, OSCILLATOR FREQUENCY (Hz)
Figure 2. Timing Resistor versus
Oscillator Frequency
1.0 M
55
50
10 k
100
pF
200
500 pF
pF
20 k
50 k 100 k 200 k
500 k 1.0 M
fosc, OSCILLATOR FREQUENCY (Hz)
Figure 3. Output Deadtime versus
Oscillator Frequency
2.55 V
2.5 V
VCC = 15 V
AV = −1.0
TA = 25°C
3.0 V
2.5 V
VCC = 15 V
AV = −1.0
TA = 25°C
2.45 V
0.5 ms/DIV
Figure 4. Error Amp Small Signal
Transient Response
2.0 V
1.0 ms/DIV
Figure 5. Error Amp Large Signal
Transient Response
100 0
VCC = 15 V
80
Gain
VO = 2.0 V to 4.0 V
RL = 100 K
30
TA = 25°C
60 60
40 90
Phase
20 120
0 150
− 20
10
180
100 1.0 k 10 k 100 k 1.0 M 10 M
f, FREQUENCY (Hz)
Figure 6. Error Amp Open Loop Gain and
Phase versus Frequency
1.2
VCC = 15 V
1.0
0.8 TA = 25°C
0.6
TA = 125°C
0.4 TA = −55°C
0.2
0
0 2.0 4.0 6.0 8.0
VO, ERROR AMP OUTPUT VOLTAGE (V)
Figure 7. Current Sense Input Threshold
versus Error Amp Output Voltage
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UC2844 전자부품, 판매, 대치품
UC3844, UC3845, UC2844, UC2845
OPERATING DESCRIPTION
The UC3844, UC3845 series are high performance, fixed
frequency, current mode controllers. They are specifically
designed for OffLine and DCtoDC converter
applications offering the designer a cost effective solution
with minimal external components. A representative block
diagram is shown in Figure 16.
Oscillator
The oscillator frequency is programmed by the values
selected for the timing components RT and CT. Capacitor CT
is charged from the 5.0 V reference through resistor RT to
approximately 2.8 V and discharged to 1.2 V by an internal
current sink. During the discharge of CT, the oscillator
generates an internal blanking pulse that holds the center
input of the NOR gate high. This causes the Output to be in
a low state, thus producing a controlled amount of output
deadtime. An internal flipflop has been incorporated in the
UCX844/5 which blanks the output off every other clock
cycle by holding one of the inputs of the NOR gate high. This
in combination with the CT discharge period yields output
deadtimes programmable from 50% to 70%. Figure 2 shows
RT versus Oscillator Frequency and Figure 3, Output
Deadtime versus Frequency, both for given values of CT.
Note that many values of RT and CT will give the same
oscillator frequency but only one combination will yield a
specific output deadtime at a given frequency.
In many noise sensitive applications it may be desirable to
frequencylock the converter to an external system clock.
This can be accomplished by applying a clock signal to the
circuit shown in Figure 18. For reliable locking, the
freerunning oscillator frequency should be set about 10%
less than the clock frequency. A method for multi unit
synchronization is shown in Figure 19. By tailoring the
clock waveform, accurate Output duty cycle clamping can
be achieved to realize output deadtimes of greater than 70%.
Error Amplifier
A fully compensated Error Amplifier with access to the
inverting input and output is provided. It features a typical
dc voltage gain of 90 dB, and a unity gain bandwidth of
1.0 MHz with 57 degrees of phase margin (Figure 6). The
noninverting input is internally biased at 2.5 V and is not
pinned out. The converter output voltage is typically divided
down and monitored by the inverting input. The maximum
input bias current is 2.0 mA which can cause an output
voltage error that is equal to the product of the input bias
current and the equivalent input divider source resistance.
The Error Amp Output (Pin 1) is provide for external loop
compensation (Figure 29). The output voltage is offset by
two diode drops (1.4 V) and divided by three before it
connects to the inverting input of the Current Sense
Comparator. This guarantees that no drive pulses appear at
the Output (Pin 6) when Pin 1 is at its lowest state (VOL).
This occurs when the power supply is operating and the load
is removed, or at the beginning of a softstart interval
(Figures 21, 22). The Error Amp minimum feedback
resistance is limited by the amplifier’s source current
(0.5 mA) and the required output voltage (VOH) to reach the
comparator’s 1.0 V clamp level:
Rf(min)
3.0
(1.0 V) +
0.5 mA
1.4
V=
8800
W
Current Sense Comparator and PWM Latch
The UC3844, UC3845 operate as a current mode
controller, whereby output switch conduction is initiated by
the oscillator and terminated when the peak inductor current
reaches the threshold level established by the Error
Amplifier Output/Compensation (Pin 1). Thus the error
signal controls the inductor current on a cyclebycycle
basis. The current Sense Comparator PWM Latch
configuration used ensures that only a single pulse appears
at the Output during any given oscillator cycle. The inductor
current is converted to a voltage by inserting the ground
referenced sense resistor RS in series with the source of
output switch Q1. This voltage is monitored by the Current
Sense Input (Pin 3) and compared a level derived from the
Error Amp Output. The peak inductor current under normal
operating conditions is controlled by the voltage at pin 1
where:
Ipk =
V(Pin 1) 1.4 V
3 RS
Abnormal operating conditions occur when the power
supply output is overloaded or if output voltage sensing is
lost. Under these conditions, the Current Sense Comparator
threshold will be internally clamped to 1.0 V. Therefore the
maximum peak switch current is:
Ipk(max) =
1.0 V
RS
When designing a high power switching regulator it
becomes desirable to reduce the internal clamp voltage in
order to keep the power dissipation of RS to a reasonable
level. A simple method to adjust this voltage is shown in
Figure 20. The two external diodes are used to compensate
the internal diodes yielding a constant clamp voltage over
temperature. Erratic operation due to noise pickup can result
if there is an excessive reduction of the Ipk(max) clamp
voltage.
A narrow spike on the leading edge of the current
waveform can usually be observed and may cause the power
supply to exhibit an instability when the output is lightly
loaded. This spike is due to the power transformer
interwinding capacitance and output rectifier recovery time.
The addition of an RC filter on the Current Sense Input with
a time constant that approximates the spike duration will
usually eliminate the instability; refer to Figure 24.
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