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PDF HCF4014B Data sheet ( Hoja de datos )
| Número de pieza | HCF4014B | |
| Descripción | 8-STAGE STATIC SHIFT REGISTERS | |
| Fabricantes | STMicroelectronics | |
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HCC/HCF4014B
HCC/HCF4021B
8-STAGE STATIC SHIFT REGISTERS
4014B SYNCHRONOUS PARALLEL OR
SERIAL INPUT/SERIAL OUTPUT
4021B ASYNCHRONOUS PARALLEL
INPUT OR SYNCHRONOUS
SERIAL INPUT/SERIAL OUTPUT
. MEDIUM-SPEED OPERATION-12MHz (typ.)
CLOCK RATE AT VDD – VSS = 10V
. FULLY STATIC OPERATION
. 8 MASTER-SLAVE FLIP-FLOPS PLUS OUT-
PUT BUFFERING AND CONTROL GATING
. QUIESCENT CURRENT SPECIFIED TO 20V
FOR HCC DEVICE
. 5V, 10V AND 15V PARAMETRIC RATINGS
. INPUT CURRENT OF 100nA AT 18V AND 25°C
FOR HCC DEVICE
. 100% TESTED FOR QUIESCENT CURRENT
. MEETS ALL REQUIREMENTS OF JEDECTEN-
TATIVE STANDARD No 13A, ”STANDARD
SPECIFICATIONS FOR DESCRIPTION OF ”B”
SERIES CMOS DEVICES”
DESCRIPTION
The HCC4014B, HCC4021B (extended temperatu-
re range) and the HCF4014B, HCF4021B (interme-
diate temperature range) are monolithic integrated
circuits, available in 16-lead dual in-line plastic or ce-
ramic package and plastic micro package. The
HCC/HCF4014B and HCC/HCF4021B series types
are 8-stage parallel-or serial-input/serial-output re-
gisters having common CLOCK and PARAL-
LEL/SERIAL CONTROL inputs, a single SERIAL
data input, and individual parallel ”JAM” inputs to
each register stage. Each register stage is a D type,
master-slave flip-flop in addition to an output from
stage 8, ”Q” outputs are also available from stages
6 and 7. Parallel as well as serial entry is made into
the register synchronously with the positive clock li-
ne transition in the HCC/HCF4014B. In the
HCC/HCF4021B serial entry is synchronous with
the clock but parallel entry is asynchronous. In both
types, entry is controlled by the PARALLEL/SERIAL
CONTROL input. When the PARALLEL/SERIAL
CONTROL input is low, data is serially shifted into
the 8-stage register synchronously with the positive
transition of the clock line. When the PARAL-
LEL/SERIAL CONTROL input is high, data is jam-
med into the 8-stage register via the parallel input
lines and synchronous with the positive transition of
the clock line. In the HCC/HCF4021B, the CLOCK
input of the internal stage is ”forced” whenasynchro-
nous parallel entry is made. Register expansion
using multiple package is permitted.
EY
(Plastic Package)
F
(Ceramic Package)
M1
(Micro Package)
C1
(Plastic Chip Carrier)
ORDER CODES :
HCC40XXBF
HC F 40X XB M1
HCF40XXBEY
HC F 40X XB C 1
PIN CONNECTIONS
November 1996
1/13
1 page  
HCC/HCF4014B/4021B
STATIC ELECTRICAL CHARACTERISTICS (continued)
Symbol Parameter
Test Conditions
Value
V I V O |I O | V D D T Lo w*
25°C
T High*
(V) (V) (µA) (V) Min. Max. Min. Typ. Max. Min. Max.
I OH Output
0/ 5 2.5
Drive
Current
HCC 0/ 5
Types 0/10
4.6
9.5
5 –2
5 – 0.64
10 – 1.6
– 1.6 – 3.2
– 0.51 – 1
– 1.3 – 2.6
– 1.15
– 0.36
– 0.9
0/15 13.5
15 – 4.2
– 3.4 – 6.8
– 2.4
0/ 5 2.5
5 – 1.53
– 1.36 – 3.2
– 1.1
HCF 0/ 5
Types 0/10
4.6
9.5
5 – 0.52
10 – 1.3
– 0.44 – 1
– 1.1 – 2.6
– 0.36
– 0.9
0/15 13.5
15 – 3.6
– 3.0 – 6.8
– 2.4
I OL Output
0/ 5 0.4
Sink
Current
HCC
Types
0/10
0.5
0/15 1.5
5 0.64
10 1.6
15 4.2
0.51 1
1.3 2.6
3.4 6.8
0.36
0.9
2.4
I IH, IIL
Input
Leakage
Current
0/ 5
HCF
Types
0/10
0/15
HCC 0/18
Types
HCF 0/15
Types
0.4
0.5
1.5
Any Input
5 0.52
0.44 1
0.36
10 1.3
1.1 2.6
0.9
15 3.6
3.0 6.8
2.4
18
± 0.1
±10– 5 ± 0.1
±1
15
± 0.3
±10– 5 ± 0.3
±1
CI Input Capacitance
Any Input
5 7.5
* TLow = – 55°C for HCC device : – 40°C for HCF device.
* THigh = + 125°C for HCC device : + 85°C for HCF device.
The Noise Margin for both ”1” and ”0” level is : 1V min. with VDD = 5V, 2V min. with VDD = 10V, 2.5 V min. with VDD = 15V.
Unit
mA
mA
µA
pF
DYNAMIC ELECTRICAL CHARACTERISTICS (T amb = 25°C, CL = 50pF, RL = 200kΩ,
typical temperature coefficient for all VDD = 0.3%/°C values, all input rise and fall time = 20ns)
Symbol
Parameter
CLOCKED OPERATION
Test Conditions
V al ue
V D D (V) Min. Typ. Max.
Unit
tP L H, tP HL Propagation Delay Time
5 160 320
10
80 160
ns
15 60 120
t THL , tT L H Transition Time
5 100 200
10 50 100 ns
15 40 80
fCL * Maximum Clock Input Frequency
5 36
10 6 12
MHz
15 8.5 17
tW Clock Pulse Width
5 180 90
10 80 40
ns
15 50 25
* If more than one unit is cascaded trCL should be made less than or equal to the sum of the transition time and the fixed propagation delay of
the output of the driving stage of the estimated capacitive load.
5/13
5 Page 
DIM.
A
a1
a2
b
b1
C
c1
D
E
e
e3
F
G
L
M
S
HCC/HCF4014B/4021B
SO16 (Narrow) MECHANICAL DATA
MIN.
0.1
0.35
0.19
9.8
5.8
3.8
4.6
0.5
mm
TYP.
0.5
1.27
8.89
MAX.
1.75
0.2
1.65
0.46
0.25
MIN.
0.004
0.013
0.007
45° (typ.)
10 0.385
6.2 0.228
4.0 0.149
5.3 0.181
1.27 0.019
0.62
8° (max.)
inch
TYP.
0.019
0.050
0.350
MAX.
0.068
0.007
0.064
0.018
0.010
0.393
0.244
0.157
0.208
0.050
0.024
P013H
11/13
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet HCF4014B.PDF ] | |
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