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T40N03G 데이터시트 PDF




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기능 Power MOSFET ( Transistor )
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T40N03G 데이터시트, 핀배열, 회로
NTD40N03R
Power MOSFET
45 A, 25 V, NChannel DPAK
Features
Planar HD3e Process for Fast Switching Performance
Low RDS(on) to Minimize Conduction Loss
Low Ciss to Minimize Driver Loss
Low Gate Charge
Optimized for High Side Switching Requirements in
HighEfficiency DCDC Converters
These are PbFree Devices
MAXIMUM RATINGS (TJ = 25°C unless otherwise specified)
Parameter
Symbol Value
Unit
DraintoSource Voltage
GatetoSource Voltage Continuous
Thermal Resistance JunctiontoCase
Total Power Dissipation @ TC = 25°C
Drain Current
Continuous @ TC = 25°C, Chip
Continuous @ TA = 25°C, Limited by Wires
Single Pulse (tp 10 ms)
Thermal Resistance JunctiontoAmbient
(Note 1)
Total Power Dissipation @ TA = 25°C
Drain Current Continuous @ TA = 25°C
Thermal Resistance JunctiontoAmbient
(Note 2)
Total Power Dissipation @ TA = 25°C
Drain Current Continuous @ TA = 25°C
Operating and Storage Temperature Range
VDSS
VGS
RPqDJC
ID
ID
ID
RqJA
PD
ID
RqJA
PD
ID
TJ, Tstg
25
±20
3.0
50
45
32
100
71.4
2.1
9.2
100
1.5
7.8
55 to
175
Vdc
Vdc
°C/W
W
A
A
A
°C/W
W
A
°C/W
W
A
°C
Maximum Lead Temperature for Soldering
Purposes, 1/8 in from case for 10 seconds
TL 260 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. When surface mounted to an FR4 board using 0.5 sq. in pad size.
2. When surface mounted to an FR4 board using minimum recommended
pad size.
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45 AMPERES, 25 VOLTS
RDS(on) = 12.6 mW (Typ)
NCHANNEL
D
G
S
4
4
12
3
CASE 369AA
DPAK
(Surface Mount)
STYLE 2
1
2
3
CASE 369D
DPAK
(Straight Lead)
STYLE 2
MARKING DIAGRAM
& PIN ASSIGNMENTS
4 Drain
4 Drain
1
Gate
2
Drain
3
Source
1
Gate
2
Drain
3
Source
Y
WW
T40N03
G
= Year
= Work Week
= Device Code
= PbFree Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2010
July, 2010 Rev. 7
1
Publication Order Number:
NTD40N03R/D




T40N03G pdf, 반도체, 판매, 대치품
NTD40N03R
1000
800 Ciss
VDS = 0 V VGS = 0 V
Crss
600
TJ = 25°C
Ciss
400
Coss
200
Crss
0
10
5 VGS 0 VDS 5
10 15 20
GATETOSOURCE OR DRAINTOSOURCE VOLTAGE
(VOLTS)
Figure 7. Capacitance Variation
100
VDS = 10 V
ID = 10 A
VGS = 10 V
tr
td(off)
10
td(on)
tf
1
1 10 100
RG, GATE RESISTANCE (W)
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
8
6
4
Q1
QT
Q2
VGS
2
ID = 10 A
TJ = 25°C
0
0246 8
Qg, TOTAL GATE CHARGE (nC)
Figure 8. GatetoSource and
DraintoSource Voltage versus Total Charge
20
18 VGS = 0 V
16 TJ = 25°C
14
12
10
8
6
4
2
0
0 0.2 0.4 0.6 0.8 1.0
VSD, SOURCETODRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus
Current
100
SINGLE PULSE
VGS = 20 V
TC = 25°C
10 ms
100 ms
10
1 ms
1
0.1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
10 ms
dc
1 10
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)
100
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
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4

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T40N03G 전자부품, 판매, 대치품
NTD40N03R
PACKAGE DIMENSIONS
DPAK (SINGLE GAUGE)
CASE 369D01
ISSUE B
V
S
T
SEATING
PLANE
B
R
4
123
A
K
C
E
F
G
J
D 3 PL
0.13 (0.005) M T
H
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
INCHES MILLIMETERS
DIM MIN MAX MIN MAX
Z A 0.235 0.245 5.97 6.35
B 0.250 0.265 6.35 6.73
C 0.086 0.094 2.19 2.38
D 0.027 0.035 0.69 0.88
E 0.018 0.023 0.46 0.58
F 0.037 0.045 0.94 1.14
G 0.090 BSC
2.29 BSC
H 0.034 0.040 0.87 1.01
J 0.018 0.023 0.46 0.58
K 0.350 0.380 8.89 9.65
R 0.180 0.215 4.45 5.45
S 0.025 0.040 0.63 1.01
V 0.035 0.050 0.89 1.27
Z 0.155 −−− 3.93 −−−
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
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associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 3036752175 or 8003443860 Toll Free USA/Canada
Fax: 3036752176 or 8003443867 Toll Free USA/Canada
N. American Technical Support: 8002829855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81357733850
http://onsemi.com
7
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NTD40N03R/D

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T40N03G

Power MOSFET ( Transistor )

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