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PDF ST16C554D Data sheet ( Hoja de datos )
| Número de pieza | ST16C554D | |
| Descripción | 2.97V TO 5.5V QUAD UART | |
| Fabricantes | Exar Corporation | |
| Logotipo |  |
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ST16C554/554D
2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO
JUNE 2006
REV. 4.0.1
GENERAL DESCRIPTION
The ST16C554/554D (554) is a quad Universal
Asynchronous Receiver and Transmitter (UART) with
16 bytes of transmit and receive FIFOs, selectable
receive FIFO trigger levels and data rates of up to 1.5
Mbps. Each UART has a set of registers that provide
the user with operating status and control, receiver
error indications, and modem serial interface
controls. An internal loopback capability allows
onboard diagnostics. The 554 is available in a 64-pin
LQFP and a 68-pin PLCC package. The 64-pin
package only offers the 16 mode interface, but the
68-pin package offers an additional 68 mode
interface which allows easy integration with Motorola
processors. The ST16C554CQ64 (64-pin) offers
three state interrupt output while the
ST16C554DCQ64 provides continuous interrupt
output. The 554 combines the package interface
modes of the 16C554 and 68C554 on a single
integrated chip.
FEATURES
• Pin-to-pin compatible with the industry standard
ST16C454, ST68C454, ST68C554, TI’s
TL16C554A and Philips’ SC16C554B
• Intel or Motorola Data Bus Interface select
• Four independent UART channels
■ Register Set Compatible to 16C550
■ Data rates of up to 1.5 Mbps at 5 V
■ Data rates of up to 500 Kbps at 3.3V
■ 16 byte Transmit FIFO
■ 16 byte Receive FIFO with error tags
■ 4 Selectable RX FIFO Trigger Levels
■ Full modem interface
• 2.97V to 5.5V supply operation
• Crystal oscillator or external clock input
APPLICATIONS
• Portable Appliances
• Telecommunication Network Routers
• Ethernet Network Routers
• Cellular Data Devices
• Factory Automation and Process Controls
FIGURE 1. ST16C554 BLOCK DIAGRAM
A2:A0
D7:D0
IOR#
IOW#
CSA#
CSB#
CSC#
CSD#
INTA
INTB
INTC
INTD
TXRDY#A-D
RXRDY#A-D
Reset
16/68#
INTSEL
Data Bus
Interface
UART Channel A
UART
Regs
BRG
16 Byte TX FIFO
TX & RX
IR
ENDEC
16 Byte RX FIFO
UART Channel B
(same as Channel A)
UART Channel C
(same as Channel A)
UART Channel D
(same as Channel A)
Crystal Osc / Buffer
2.97 V to 5.5 V VCC
GND
TXA, RXA, IRTXA, DTRA#,
DSRA#, RTSA#, CTSA#,
CDA#, RIA#
TXB, RXB, IRTXB, DTRB#,
DSRB#, RTSB#, CTSB#,
CDB#, RIB#
TXC, RXC, IRTXC, DTRC#,
DSRC#, RTSC#, CTSC#,
CDC#, RIC#
TXD, RXD, IRTXD, DTRD#,
DSRD#, RTSD#, CTSD#,
CDD#, RID#
XTAL1
XTAL2
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
1 page  
REV. 4.0.1
Pin Description
ST16C554/554D
2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO
NAME
64-LQFP
PIN #
68-PLCC
PIN#
TYPE
DESCRIPTION
DTRA#
DTRB#
DTRC#
DTRD#
3
15
34
46
12 O UART channels A-D Data-Terminal-Ready (active low) or general purpose out-
24 put. If these outputs are not used, leave them unconnected.
46
58
DSRA#
DSRB#
DSRC#
DSRD#
1
17
32
48
10 I UART channels A-D Data-Set-Ready (active low) or general purpose input. This
26 input should be connected to VCC when not used. This input has no effect on
44 the UART.
60
CDA#
CDB#
CDC#
CDD#
64
18
31
49
9 I UART channels A-D Carrier-Detect (active low) or general purpose input. This
27 input should be connected to VCC when not used. This input has no effect on
43 the UART.
61
RIA#
RIB#
RIC#
RID#
63
19
30
50
8 I UART channels A-D Ring-Indicator (active low) or general purpose input. This
28 input should be connected to VCC when not used. This input has no effect on
42 the UART.
62
ANCILLARY SIGNALS
XTAL1
25
35 I Crystal or external clock input.
XTAL2
26
36 O Crystal or buffered clock output.
16/68#
-
31 I Intel or Motorola Bus Select (input with internal pull-up).
When 16/68# pin is HIGH, 16 or Intel Mode, the device will operate in the Intel
bus type of interface.
When 16/68# pin is LOW, 68 or Motorola mode, the device will operate in the
Motorola bus type of interface.
Motorola bus interface is not available on the 64 pin package.
RESET
(RESET#)
27
37 I When 16/68# pin is HIGH for Intel bus interface, this input becomes the Reset
pin (active high). In this case, a 40 ns minimum HIGH pulse on this pin will
reset the internal registers and all outputs. The UART transmitter output will be
held HIGH, the receiver input will be ignored and outputs are reset during reset
period (Table 13). When 16/68# pin is at LOW for Motorola bus interface, this
input becomes Reset# pin (active low). This pin functions similarly, but instead
of a HIGH pulse, a 40 ns minimum LOW pulse will reset the internal registers
and outputs.
Motorola bus interface is not available on the 64 pin package.
VCC
4, 21, 35, 13, 30, Pwr 2.97V to 5.5V power supply.
52 47, 64
GND
14, 28, 6, 23, 40, Pwr Power supply common, ground.
45, 61
57
N.C.
-
-
No Connection. These pins are not used in either the Intel or Motorola bus
modes.
Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.
5
5 Page 
REV. 4.0.1
FIGURE 5. BAUD RATE GENERATOR
To Other
Channels
XTAL1
XTAL2
Crystal
Osc /
Buffer
ST16C554/554D
2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO
DLL and DLM
Registers
Programmable Baud
Rate Generator Logic
16 X Sampling
Rate Clock
to Transmitter
and Receiver
TABLE 6: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK
OUTPUT Data Rate OUTPUT Data Rate
MCR Bit-7=1
MCR Bit-7=0 DIVISOR FOR 16x DIVISOR FOR 16x
Clock (Decimal) Clock (HEX)
(DEFAULT)
DLM
PROGRAM
VALUE (HEX)
DLL
PROGRAM
VALUE (HEX)
DATA RATE
ERROR (%)
100 400 2304 900 09 00 0
600
2400
384 180 01 80 0
1200
4800 192 C0 00 C0 0
2400 9600 96 60 00 60 0
4800
19.2k
48
30 00 30 0
9600
38.4k
24
18 00 18 0
19.2k
76.8k
12
0C 00 0C 0
38.4k
153.6k
6
06 00 06 0
57.6k
230.4k
4
04 00 04 0
115.2k
460.8k
2
02 00 02 0
230.4k
921.6k
1
01 00 01 0
2.9 Transmitter
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 16 bytes of FIFO which
includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X internal
sampling clock. A bit time is 16X clock periods. The transmitter sends the start-bit followed by the number of
data bits, inserts the proper parity-bit if enabled, and adds the stop-bit(s). The status of the FIFO and TSR are
reported in the Line Status Register (LSR bit-5 and bit-6).
2.9.1 Transmit Holding Register (THR) - Write Only
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input
register to the transmit FIFO of 16 bytes when FIFO operation is enabled by FCR bit-0. Every time a write
operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data
location.
11
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| PDF Descargar | [ Datasheet ST16C554D.PDF ] | |
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