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PDF ZN425E8 Data sheet ( Hoja de datos )
| Número de pieza | ZN425E8 | |
| Descripción | 8-BIT D-A/A-D CONVERTER | |
| Fabricantes | GEC Plessey | |
| Logotipo |  |
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ZN425E8
8-BIT D-A/A-D CONVERTER
MAY 1994
DS3005-2.0
The ZN425 is a monolithic 8-bit D-A converter
containing an R-2R ladder network of diffused resistors with
precision bipolar switches, and in addition a counter and a
2.5V precision voltage reference. The counter is a powerful
addition which allows a precision staircase to be generated
very simply by clocking the counter.
FEATURES
s ±1/2 LSB Linearity Error
s 0°C to +70°C
s TTL and 5V CMOS Compatible
s Single +5V Supply
s Settling Time (D-A) 1µs Typical
s Conversion Time (A-D) 1ms Typical, using Ramp
and Compare Technique
s Extra Components Required
D-A: Reference Capacitor (Direct Voltage Output
through 10kOhms Typ.)
A-D: Comparator, Gate, Clock and Reference
Capacitor
ORDERING INFORMATION
Ambient operating temperature 0°C to +70°C
PackageDP16
GROUND
INPUT SELECT
COUNTER RESET
CLOCK
BIT 8
BIT 7
BIT 6
+VCC
1
2
3
4
5
6
7
8
16 VREF OUTPUT
15 VREF INPUT
14 ANALOG OUTPUT
13 BIT 1 (MSB)
12 BIT 2
11 BIT 3
10 BIT 4
9 BIT 5
DP16
Fig.1 Pin connections (not to scale) - top view
ABSOLUTE MAXIMUM RATINGS
Supply voltage, VCC
Max. voltage, logic and VREF inputs
Operating temperature range
Storage temperature range
+7.0V
+5.5V See note 3
0°C to +70°C
-55°C to +125°C
Fig.2 System diagram
1 page  
2. 8-bit A-D Converter
A counter type ADC can be constructed by adding a
voltage comparator and a latch as in Fig.6. On the negative
edge of the CONVERT COMMAND pulse (15µs minimum)
the counter is set to zero and the STATUS latch to logical
1.On the positive edge the gate is opened, enabling clock
pulses to be fed to the counter input of the ZN425. The
minimum negative clock pulse width of the ZN425 is 100ns.
The analog output of the ZN425 ramps until it equals the
voltage on the other input of the comparator. At this point the
comparator output goes low and resets the STATUS to inhibit
further clock pulses. The logical 0 from the status latch
indicates that the 8-bit digital output is a valid representation
of the analog input voltage.
ZN425
A small capacitor of 47pF is added to the ZN425 output
to stop any positive going glitches prematurely resetting the
status latch. This capacitance is in parallel with the ZN425
output capacitance (20-30pF) and they form a time constant
with the ZN425 output resistance (10kΩ). This time constant
is the main limit to the maximum clock frequency. With a fast
comparator the clock frequency can be up to 300kHz. The
conversion time varies with the input being a maximum for
full-scale input.
Maximum conversion time =
256
clock frequency in Hz seconds
Fig.6 8-bit A-D converter
3. Precision Ramp generator
The inclusion of an 8-bit binary counter on the chip gives
the ZN425 a useful ramp generator function. The circuit, Fig.
7, uses the same buffer stages as the D-A converter. The
calibration procedure is also the same. Holding pin 2 low will
set all bits to ON and if RESET is taken low with pin 2 high all
the bits are turned OFF. If the end voltages of the ramp are
not required to be set accurately then the buffer stage could
be omitted and the voltage ramp will appear directly at pin 14.
5
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