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PDF UBA2037 Data sheet ( Hoja de datos )

Número de pieza UBA2037
Descripción Full bridge control IC
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



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No Preview Available ! UBA2037 Hoja de datos, Descripción, Manual

UBA2037
Full bridge control IC for HID general lighting
Rev. 01 — 30 October 2008
Product data sheet
1. General description
The UBA2037 is a high voltage monolithic Integrated Circuit (IC) manufactured in a High
Voltage Silicon On Insulator (HVSOI) process. This circuit is designed for driving
MOSFETs in a full bridge configuration. In addition, it features a disable function, an
internal adjustable oscillator and an external clock input function with a high-voltage level
shifter for driving the bridge. To guarantee an accurate 50 % duty cycle, the oscillator
signal can be passed through a divider before being fed to the output drivers.
The UBA2037 is especially suitable for High Intensity Discharge (HID) lamp drivers for
projectors and general lighting applications.
2. Features
I Full bridge driver circuit
I Integrated bootstrap diodes
I 464 V integrated high voltage level shift function to drive HID lamps below ground level
I 550 V series regulator input to make the internal supply
I 550 V maximum bridge voltage
I Accurate bridge disable function
I Input for start-up delay
I Adjustable oscillator frequency
I Selectable frequency divider
I Predefined bridge position during start-up
I Adaptive non-overlap
3. Applications
I The UBA2037 can drive (via the power MOSFETs) any kind of load in a full bridge
configuration.
I The circuit is especially designed as a commutator controller for HID lamps in
projectors and general lighting applications.

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UBA2037 pdf
NXP Semiconductors
UBA2037
Full bridge control IC for HID general lighting
Table 3. Driver
Gate driver output voltages as function of the logical levels at the pins BD, SU, DD and CLK.
Device
state
BD SU DD CLK GHL
GHR
GLL
GLR
Start-up 1 -
state
0-
--
--
0 (= VSHL)
0 (= VSHL)
0 (= VSHR)
0 (= VSHR)
0 (= VPGND) 0 (= VPGND)
1 (= VVDD) 1 (= VVDD)
Oscillation 1 -
--
state
00 - -
0 (= VSHL)
0 (= VSHL)
0 (= VSHR)
0 (= VSHR)
0 (= VPGND) 0 (= VPGND)
1 (= VVDD) 1 (= VVDD)
01
11
0 (= VSHL) 1 (= VFSR) 1 (= VVDD) 0 (= VPGND)
01
01
10
1 (= VFSL) 0 (= VSHR) 0 (= VPGND) 1 (= VVDD)
0[1] 1 0[2] GHL
GHR
GLL
GLR
[1] If pin DD = 0 the bridge enters the state (oscillation state and pin BD = 0 and pin SU = 1) in the predefined
position: VGHL = VFSL, VGLR = VVDD, VGLL = VPGND, and VGHR = VSHR.
[2] Only if the level of pin CLK changes from logical 1 to 0, the level of outputs GHL, GHR, GLL and GLR
changes.
If there is no external clock available, the internal oscillator can be used. The design
equation for the bridge oscillator frequency is shown in Equation 1.
f bridge = -K----o---s--c---×-----R----1o---s--c---×-----C-----o--s---c
(1)
Rosc and Cosc are external components connected to the RC pin (Rosc connected to pin
VDD and Cosc connected to pin SGND). In this situation the pins VDD(CLK), CLK and
VSS(CLK) can be connected to SGND.
The clock signal, coming from either pin RC or pin CLK, can be divided by two in order to
obtain a 50 % duty-cycle gate drive signal. This can be achieved by applying a voltage to
the DD input lower than VIL(DD) (e.g. connect pin DD to pin SGND).
7.4 Non-overlap time
In the full bridge configuration the non-overlap time is defined as the time between turning
off the two conducting MOSFETs and turning on the two other MOSFETs. The
non-overlap time is realized by means of an adaptive non overlap circuit. With an adaptive
non-overlap, the application determines the duration of the non overlap and makes the
non-overlap time optimal for each frequency. The non-overlap time is determined by the
duration of the falling slope of the relevant half bridge voltage. The occurrence of a slope
is sensed internally. The minimum non-overlap time is internally fixed.
7.5 Start-up delay
A simple RC filter (R between pin VDD and pin SU; C between pin SU and pin SGND) or
a control signal from a processor can be used to make a start-up delay. This can be
beneficial for those applications in which building up the high voltage takes a larger
amount of time: A start-up delay will ensure that the HID system will not start up before
this high voltage has been reached.
UBA2037_1
Product data sheet
Rev. 01 — 30 October 2008
© NXP B.V. 2008. All rights reserved.
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UBA2037 arduino
NXP Semiconductors
UBA2037
Full bridge control IC for HID general lighting
SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm
SOT341-1
y
Z
28
D
pin 1 index
1
e
c
15
EA
X
HE v M A
14
wM
bp
A2
A1
Q
(A3)
A
Lp
L
detail X
θ
0 2.5 5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c D(1) E(1) e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
2
0.21
0.05
1.80
1.65
0.25
0.38
0.25
0.20
0.09
10.4
10.0
5.4
5.2
0.65
7.9
7.6
1.25
1.03
0.63
0.9
0.7
0.2 0.13 0.1
1.1
0.7
8o
0o
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
OUTLINE
VERSION
SOT341-1
IEC
REFERENCES
JEDEC
JEITA
MO-150
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Fig 6. Package outline SSOP28 (SOT341-1)
UBA2037_1
Product data sheet
Rev. 01 — 30 October 2008
© NXP B.V. 2008. All rights reserved.
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