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MGA-637P8 데이터시트 PDF




AVAGO에서 제조한 전자 부품 MGA-637P8은 전자 산업 및 응용 분야에서
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부품번호 MGA-637P8 기능
기능 High Linearity Low Noise Amplifier
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MGA-637P8 데이터시트, 핀배열, 회로
MGA-637P8
High Linearity Low Noise Amplifier
Data Sheet
Description
Avago Technologies’ MGA-637P8 is an economical, easy-
to-use GaAs MMIC Low Noise Amplifier (LNA). This LNA
has low noise and high linearity achieved through the
use of Avago Technologies’ proprietary 0.25 m GaAs
Enhancement-mode pHEMT process. It is housed in the
miniature 2.0 x 2.0 x 0.75 mm3 8-pin Dual-Flat-Non-Lead
(DFN) package. The device is designed for optimum use
from 1.5 GHz up to 2.5 GHz. The compact footprint and
low profile coupled with low noise, high gain and high
linearity make this an ideal choice as a low noise amplifier
for cellular infrastructure applications such as LTE, GSM,
CDMA, W-CDMA, CDMA2000 & TD-SCDMA. For optimum
performance at lower frequency from 450 MHz up to
1.5 GHz, MGA-636P8 is recommended. For optimum
performance at higher frequency from 2.5 GHz up to
4 GHz, MGA-638P8 is recommended. All these 3 products,
MGA-636P8, MGA-637P8 and MGA-638P8 share the same
package and pinout configuration.
Pin Configuration and Package Marking
2.0 x 2.0 x 0.75 mm3 8-lead DFN
[1] [8]
[2] 37X [7]
[3] [6]
[4] [5]
[8] [1]
[7] [2]
[6] GND [3]
[5] [4]
TOP VIEW
Pin 1 – Not Used
Pin 2 – RFinput
Pin 3 – Vbias2
Pin 4 – Not Used
Center paddle – GND
BOTTOM VIEW
Pin 5 – Vbias1
Pin 6 – PwrDwn
Pin 7 – RFoutput
Pin 8 – Not Used
Note:
Package marking provides orientation and identification
“37” = Product Code
“X” = Month Code
It is recommended to ground Pin1, 4 and 8 which are Not Used.
Features
 High linearity performance.
 Low Noise Figure.
 GaAs E-pHEMT Technology[1].
 Low cost small package size.
 Integrated with active bias and option to access FET
gate.
 Integrated power down control pin.
Specifications
1.7 GHz; 4.8 V, 75 mA
 17.3 dB Gain
 0.52 dB Noise Figure
 11 dB Input Return Loss
 22.5 dBm Input IP3
 21.9 dBm Output Power at 1 dB gain compression
Applications
 Cellular infrastructure applications such as LTE, GSM,
CDMA, W-CDMA, CDMA2000 & TD-SCDMA.
 Other low noise applications.
Note:
1. Enhancement mode technology employs positive Vgs, thereby
eliminating the need of negative gate voltage associated with con-
ventional depletion mode devices.
Attention: Observe precautions for
handling electrostatic sensitive devices.
ESD Machine Model = 80 V
ESD Human Body Model = 350 V
Refer to Avago Application Note A004R:
Electrostatic Discharge, Damage and Control.




MGA-637P8 pdf, 반도체, 판매, 대치품
Demo Board Layout
Demo Board Schematic
Avago
Technologies
BTS LNA
Nov 2010
RFin L3
C1
L1
C3
Rb
R1
C5
C7
C2
L2
C4
C6
C8
RFout
L3
RFin C1
L1
C3
R1
C5
[1]
[NU]
[2]
[RFinput]
[3]
[Vbias2]
[4]
[NU]
Bias
Rb
Vdd
C6
R2
C4
[8]
[NU]
[7]
[RFoutput]
[6]
[PwrDwn]
[5]
[Vbias1]
L2
C2 RFout
C7 C8
Vbias1 PwrDwn
Figure 5. Demo Board Layout Diagram
– Recommended PCB material is 10 mils Rogers RO4350.
– Suggested component values may vary according to
layout and PCB material.
Truth Table
LNA Mode
Power Down Mode
VPwrDwn(V)
0 or open
3.3
Figure 6. Demo Board Schematic Diagram
Notes:
The schematic is shown with the assumption that similar PCB is used
for all MGA-636P8, MGA-637P8 and MGA-638P8.
Detail of the components needed for this product is shown in Table 1.
Table 1. Component list for 1.7 GHz matching
Part Size
C1 0402
C2 0402
C5, C6, C7, C8
0603
C3, C4
0402
L1, L2
0402
L3 0402
Rb 0402
R1, R2
0402
Notes:
C1, C2 are DC blocking capacitors
L1 input match for NF
L2 output match for IP3
C5, C6, C7, C8 are bypass capacitors
Rb is the biasing resistor
Value
100 pF (Murata)
150 pF (Murata)
4.7 F (Murata)
Not Used
8.2 nH (Toko)
Not Used
750 ohm (Rohm)
0 ohm (Rohm)
4
Detail Part Number
GRM1555C1H101JD01D
GRM1555C1H151JD01D
GRM188R60J475KE19D
LLP1005-FH8N2C
MCR004YZPJ751
MCR01MZPJ000

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MGA-637P8 전자부품, 판매, 대치품
Below is the table showing the MGA-637P8 Reflection Coefficient Parameters
tuned for Maximum IIP3, Vdd = 4.8 V, Idd = 75 mA.
Frequency
(GHz)
1.5
1.7
1.9
2.0
2.2
2.5
Gamma Load position
Magnitude
Angle
0.27 99.9
0.27 100
0.27 119.9
0.27 120
0.36 129.7
0.36 143.9
IIP3
(dBm)
25.3
26
27.2
28
28.7
30.2
[1]
[NU]
RFinput
Reference Plane
[2]
[RFinput]
[3]
[Vbias2]
[4]
[NU]
Bias
[8]
[NU]
[7]
[RFoutput]
RFoutput
Reference Plane
[6]
[PwrDwn]
[5]
[Vbias1]
Figure 16. RFinput and RFoutput Reference Plane
Notes:
1. The Maximum IIP3 values are calculated based on Load pull measure-
ments on approximately 100 different impedances using Focus Load pull
test system.
2. Measurements are conducted on 0.010 inch thick ROGER 4350. The input
reference plane is at the end of the RFin pin and the output reference
plane is at the end of the RFout pin as shown in Figure 16.
7

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부품번호상세설명 및 기능제조사
MGA-637P8

High Linearity Low Noise Amplifier

AVAGO
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