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W523S12 데이터시트 PDF




Winbond에서 제조한 전자 부품 W523S12은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


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부품번호 W523S12 기능
기능 HIGH FIDELITY PowerSpeech
제조업체 Winbond
로고 Winbond 로고


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W523S12 데이터시트, 핀배열, 회로
www.DataSheet4U.com
W523SXX (PRELIMINARY)
HIGH FIDELITY PowerSpeechTM
GENERAL DESCRIPTION
The W523Sxx family are programmable speech synthesis ICs that utilize Winbonds new high fidelity
voice synthesis algorithm to generate all types of voice effects with high sound quality.
The W523Sxx’ s LOAD, JUMP, MOVE and INC commands and ten programmable registers provide
powerful user-programmable functions that make this chip suitable for an extremely wide range of
speech IC applications.
The W523Sxx family includes 14 kinds of bodies which are the same except for the voice duration
shown below:
PART
NO.
W523S08 W523S10 W523S12 W523S15 W523S20 W523S25 W523S30
Duration
8 sec.
10 sec.
12 sec.
15 sec.
20 sec.
25 sec.
30 sec.
PART
NO.
Duration
W523S40
40 sec.
W523S50
50 sec.
W523S60
60 sec.
W523S70
70 sec.
W523S80
80 sec.
W523S99 W523M02
100 sec. 120 sec.
Note: The voice duration is estimated by 6.4 KHz sampling rate.
FEATURES
Operating voltage range: 2.4 – 5.5 volts for both DAC and PWM output
New high fidelity synthesis algorithm
Either PWM mode or D/A converter mode can be selected for AUD output
Provides 4 direct trigger inputs that can easily be extended to 24 matrix trigger inputs
Two trigger input debounce times (50 mS or 400 uS) can be set
Provides up to 2 LEDs and 5 STOP outputs
Flexible functions programmable through the following:
LD (Load), JP (Jump), MV (Move) and INC (Increase) commands
Four general purpose registers: R0, R1, R2 and R3
Six special purpose registers: EN0, EN1, MODE0, MODE1, STOP and PAGE
Conditional instructions: @LAST, @TGn_HIGH or LOW, where, n = 1,2,5 or 6
Speech equations
END instruction
Supports CPU interface operation
Symbolic compiler supported
Instruction cycle 400 µS typically
Section control for
Variable frequency: 4.8/6/8/12 KHz
Publication Release Date:Oct. 2000
- 1 - Revision A5




W523S12 pdf, 반도체, 판매, 대치품
W523SXX (PRELIMINARY)
power-on, an “ END” instruction should be entered in the group 32.
The interruption priority is shown as below while other trigger pins as well as JUMP (JP) command are
executing simultaneously during POI executing period:
POI > TG1F > TG1R > TG2F > TG2R > TG5F > TG5R > TG6F > TG6R > "JP" instruction.
Register Definition and Control
The register file in the W523Sxx family is composed of 10 registers, including 4 general-purpose
registers and 6 special purpose registers. They are defined to facilitate the operations for various
purposes. The default setting values of the registers are given in the following table.
REGISTER
NAME
DEFAULT SETTING
General Register
R0-R3
00100000B
Special Register
EN0
XX11XX11B
EN1 XX11XX11B
MODE0, MODE1
11111111B
STOP
XXX11111B
PAGE
00000000B
1. MODE0 Register
BIT DESCRIPTION
7 LED mode
6 LED2/STPC
pin selection
4 Debounce time
2 STPA/BUSY
pin selection
5,3,1,0 X
DEFINITION
1: Flash
0: DC
1: LED2 output
0: STPC output
1: Long
0: Short
1: STPA output
0: BUSY output
Don’ t care
The MODE0.7 bit defines the output type of LED1 and LED2 pins as Flash output (3 Hz) or DC output.
The MODE0.6 bit defines the configuration of LED2/STPC pin’ s status as LED2 output or STPC
output. The MODE0.4 bit defines the trigger pin’ s debounce time as long debounce (50 mS) or short
debounce (400 uS). The MODE0.2 bit defines the behavior of the STPA/BUSY pin as STPA output in
normal mode or BUSY signal output in CPU mode. The bits 5, 3, 1 and 0 are don’ t care bits.
-4-

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W523S12 전자부품, 판매, 대치품
W523SXX (PRELIMINARY)
Interrupt Vector Allocation
The W523Sxx provides a total of 4 trigger inputs to communicate with the outside world. Each trigger
pin can invoke 2 dedicate interrupt vectors depending on TG pins’ status (rising or falling). The table
below shows the relationship between triggers’ status and interrupt vectors.
INTERRUPT VECTOR
0
1
8
9
INTERRUPT VECTOR
4
5
12
13
32
TRIGGER SOURCE
TG1F
TG2F
TG5F
TG6F
TRIGGER SOURCE
TG1R
TG2R
TG5R
TG6R
POI
CPU Interface
The W523Sxx can communicate with an external microprocessor through a simple serial CPU
interface. The CPU interface consists of TG1, TG2 and STPA/BUSY pins, which are shown below:
TG1
(Data)
TG2
(Clock)
STPA/Busy
TDEB
Debounced OK. to clear the internal CPU
counter for preventing the system from
running away. (TG1F should be disabled.)
TCRD
AUD/SPK+
Note:
1. TDEB means the "Debounce time".
2. TCRD is the "CPU Reset Delay" time. This should be more than 2.6 µS.
3. The "Clock" frequency of the TG2 pin can be set in the range: 10 KHz - 1 MHz.
END
Busy signal will output "high" after the end of transmission. The rising timing of Busy signal is
Publication Release Date: Oct 2000
- 7 - Revision A5

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