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기능 450MHz / 600MHz MCU
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R7S910011CBG 데이터시트, 핀배열, 회로
Preliminary Datasheet
Specifications in this document are tentative and subject to
RZ/T1 Group
R01DS0228EJ0060
Rev.0.60
Nov 14, 2014
450 MHz/600MHz, MCU with ARM Cortex®-R4F and -M3*1, on-chip FPU, 747/996 DMIPS, up to 1
Mbyte of on-chip extended SRAM, Ethernet MAC, EtherCAT*1, USB 2.0 high-speed, CAN, various
communications interfaces such as an SPI multi-I/O bus controller, ∆Σ interface, safety functions,
encoder interfaces*1, and security functions*1
Features
On-chip 32-bit ARM Cortex-R4F processor
High-speed realtime control with maximum operating frequency of
450/600 MHz
Capable of 747/996 DMIPS (in operation at 450/600 MHz)
On-chip 32-bit ARM Cortex-R4F (revision r1p4)
Tightly coupled memory (TCM) with ECC: 512 Kbytes/32 Kbytes
Instruction cache/data cache with ECC: 8 Kbytes per cache
High-speed interrupt
The FPU supports addition, subtraction, multiplication, division,
multiply-and-accumulate, and square-root operations at single-
precision and double-precision.
Harvard architecture with 8-stage pipeline
Supports the memory protection unit (MPU)
ARM CoreSight architecture, includes support for debugging
through JTAG and SWD interfaces
(Oinn-pcrhoidpu3c2ts-biint cAoRrpMoCraotrintegxa-Mn3Rp-IrNoceensgsinoer )
150-MHz operating frequency
On-chip 32-bit ARM Cortex-M3 (revision r2p1)
RISC Harvard architecture with 3-stage pipeline
Supports the memory protection unit (MPU)
Low power consumption
Standby mode, sleep mode, and module stop function
On-chip extended SRAM
Up to 1 Mbyte of the on-chip extended SRAM with ECC
150 MHz
Data transfer
DMAC: 16 channels × 2 units
DMAC for the Ethernet controller: 1 channel
Event link controller
Module operations can be started by event signals rather than by
interrupt handlers.
Linked operation of modules is available even while the CPU is in
the sleep state.
Reset and power supply voltage control
Four reset sources including a pin reset
Dual power-voltage configuration: 3.3 V (I/O unit), 1.2 V
(internal)
Clock functions
External clock/oscillator input frequency: 25 MHz
CPU clock frequency: Up to 450/600 MHz
Low-speed on-chip oscillator (LOCO): 240 kHz
Independent watchdog timer
Operated by a clock signal obtained by frequency-dividing the
clock signal from the low-speed on-chip oscillator: Up to 120 kHz
Safety functions
Register write protection, input clock oscillation stop detection,
CRC, IWDTa, and A/D self-diagnosis
An error control module is incorporated to generate a pin signal
output, interrupt, or internal reset in response to errors originating
in the various modules.
Security functions (optional)*2
Boot mode with security through encryption
Encoder interfaces (optional)*3
EnDat 2.2 and BiSS-compliant interfaces
PRBG0320GA-A 17×17mm, 0.8-mm pitch
PLQP0176LD-A 20 x 20mm, 0.4-mm pitch
Various communications interfaces
Ethernet
- EtherCAT slave controller: 2 ports (for products incorporating an
R-IN engine)
- Ether-MAC: 1 port (without the switching function)
or
- Ether-MAC: 1 port (2 ports with the switching function)
USB 2.0 high-speed host/function : 1 channel
CAN (compliant with ISO11898-1): 2 channels (max.)
SCIFA with 16-byte transmission and reception FIFOs: 5 channels
I2C bus interface: 2 channels for transfer at up to 400 kbps
RSPIa: 4 channels
SPIBSC: Provides a single interface for multi-I/O compatible
serial flash memory
External address space
Buses for high-speed data transfer at 75 MHz (max.)
Support for up to 6 CS areas
8-, 16-, or 32-bit bus space is selectable per area
Up to 33 extended-function timers
16-bit TPUa (12 channels), MTU3a (9 channels), GPTa (4
channels): Input capture, output compare, PWM waveform output
16-bit CMT (6 channels), 32-bit CMTW (2 channels)
Serial sound interface (1 channel)
■ ∆Σ interface
Up to 4 ΔΣ modulators are connectable externally.
12-bit A/D converters
12 bits × 2 units (max.)
(8 channels for unit 0; 16 channels for unit 1)
Self diagnosis
Detection of analog input disconnection
Temperature sensor for measuring temperature
within the chip
General-purpose I/O ports
5-V tolerance, open drain, input pull-up
Multi-function pin controller
The locations of input/output functions for peripheral modules are
selectable from among multiple pins.
Operating temperature range
Tj = -40°C to +125°C
Note 1.
Note 2.
Note 3.
Optional
Details of these optional functions will only be given after completion of a binding non-disclosure agreement. For details, contact our sales
representative.
For details, contact our sales representative.
R01DS0228EJ0060 Rev.0.60
Nov 14, 2014
Page 1 of 51




R7S910011CBG pdf, 반도체, 판매, 대치품
Under development Preliminary document
Specifications in this document are tentative and subject to change.
RZ/T1 Group
1. Overview
Table 1.1
Outline of Specifications (3 / 7)
Classification
Timers
Module/Function
Description
16-bit timer pulse unit
(TPUa)
(16 bits × 6 channels) × 2 units*1
Maximum of 32 pulse-input/output possible
Select from among seven or eight counter-input clock signals for each channel
(with maximum operating frequency of 75 MHz)
Input capture/output compare function
Counter clear operation (synchronous clearing by compare match/input capture)
Simultaneous writing to multiple timer counters (TCNT)
Simultaneous register input/output by synchronous counter operation
Output of PWM waveforms in up to 15 phases in PWM mode
Support for buffered operation, phase-counting mode (two phase encoder input) and
cascade-connected operation (32 bits × 2 channels) depending on the channel.
PPG output trigger can be generated
Capable of generating conversion start triggers for the A/D converters
Digital noise filtering of signals from the input capture pins
Event linking by the ELC
Multifunction timer pulse
unit (MTU3a)
9 channels (16 bits × 8 channels, 32 bits × 1 channel)
Maximum of 28 pulse-input/output and 3 pulse-input possible
Select from among 9, 11, or 12 counter-input clock signals for each channel
(with maximum operating frequency of 150 MHz)
Input capture function
39 output compare/input capture registers
Counter clear operation (synchronous clearing by compare match/input capture)
Simultaneous writing to multiple timer counters (TCNT)
Simultaneous register input/output by synchronous counter operation
Buffered operation
Support for cascade-connected operation
Automatic transfer of register data
Pulse output mode
Toggle/PWM/complementary PWM/reset-synchronized PWM
Complementary PWM output mode
Outputs non-overlapping waveforms for controlling 3-phase inverters
Automatic specification of dead times
PWM duty cycle: Selectable as any value from 0% to 100%
Delay can be applied to requests for A/D conversion.
Non-generation of interrupt requests at peak or trough values of counters can be
selected.
Double buffer configuration
Reset synchronous PWM mode
Three phases of positive and negative PWM waveforms can be output with desired
duty cycles.
Phase-counting mode: 16-bit mode (channels 1 and 2); 32-bit mode (channels 1 and 2)
Counter functionality for dead-time compensation
Generation of triggers for A/D converter conversion
A/D converter start triggers can be skipped
Digital noise filter function for signals on the input capture and external counter clock
pins
PPG output trigger can be generated
Event linking by the ELC
R01DS0228EJ0060 Rev.0.60
Nov 14, 2014
Page 4 of 51

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R7S910011CBG 전자부품, 판매, 대치품
Under development Preliminary document
Specifications in this document are tentative and subject to change.
RZ/T1 Group
1. Overview
Table 1.1
Outline of Specifications (6 / 7)
Classification Module/Function
Communication Serial peripheral
function
interface (RSPIa)
Description
4 channels
RSPI transfer facility
Using the MOSI (master out slave in), MISO (master in slave out), SSL (slave select),
and RSPCK (RSPI clock) signals enables serial transfer through SPI operation (four
lines) or clock-synchronous operation (three lines)
Capable of handling serial transfer as a master or slave
Data formats
Switching between MSB first and LSB first
The number of bits in each transfer can be changed to any number of bits from 8 to 16,
or to 20, 24, or 32 bits.
128-bit buffers for transmission and reception
Up to four frames can be transmitted or received in a single transfer operation (with
each frame having up to 32 bits)
Buffered structure
Double buffers for both transmission and reception
RSPCK can be stopped automatically with the receive buffer full for master reception
Event linking by the ELC
SPI multi I/O bus
controller (SPIBSC)
Serial sound interface (SSI)
∆Σ interface (DSMIF)
12-bit A/D converter (S12ADC)
Temperature sensor
1 channel
One serial flash memory with multiple I/O bus sizes (single/dual/quad) can be
connected.
External address space read mode (built-in read cache)
SPI operating mode
Clock polarity and clock phase can be selected.
Maximum transfer rate: 300 Mbps (for quad)
1 channel
Duplex communication
Support of various serial audio formats
Support of master and slave functions
Generation of programmable word clock and bit clock
Support of 8, 16, 18, 20, 22, 24, and 32-bit data formats
Support of eight-stage FIFO for transmission and reception
Support of WS continue mode in which the SSIWS signal is not stopped.
4 channels
Up to 4 ∆Σ modulators are externally connectable
Sync filter can be selected as first, second or third order
12 bits × 2 units (unit 0: 8 channels, unit 1: 16 channels)*1
12-bit resosultion
Conversion time
Unit 0: 0.6 s per channel
Unit 1: 2.0 s per channel
Operating mode
Scan mode (single scan mode, continuous scan mode, or group scan mode)
Group A priority control (only for group scan mode)
Sample-and-hold function
Common sample-and-hold circuit included
In addition, channel-dedicated sample-and-hold function (4 channels: in unit 0 only)
included
Sampling variable
Sampling time can be set up for each channel
Self-diagnostic function
The self-diagnostic function internally generates three analog input voltages
(unit 0: VREFL0, VREFH0 × 1/2, VREFH0; unit 1: VREFL1, VREFH1 × 1/2, VREFH1)
Double trigger mode (A/D conversion data duplicated)
Detection of analog input disconnection
Three ways to start A/D conversion
Software trigger, timer (MTU3a, GPTa, TPUa) trigger, external trigger
Event linking by the ELC
1 channel
Relative precision: ±1°C
The voltage of the temperature is converted into a digital value by the 12-bit A/D
converter (unit 0).
R01DS0228EJ0060 Rev.0.60
Nov 14, 2014
Page 7 of 51

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R7S910011CBG

450MHz / 600MHz MCU

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