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PDF SGTL5000 Data sheet ( Hoja de datos )

Número de pieza SGTL5000
Descripción Low Power Stereo Codec
Fabricantes Freescale Semiconductor 
Logotipo Freescale Semiconductor Logotipo



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No Preview Available ! SGTL5000 Hoja de datos, Descripción, Manual

Freescale Semiconductor
Technical Data
Low Power Stereo Codec with
Headphone Amp
Document Number: SGTL5000
Rev. 6.0, 11/2013
SGTL5000
The SGTL5000 is a Low Power Stereo Codec with Headphone Amp
from Freescale, and is designed to provide a complete audio solution
for products needing LINEIN, MIC_IN, LINEOUT, headphone-out, and
digital I/O. Deriving it’s architecture from best in class, Freescale
integrated products that are currently on the market. The SGTL5000 is
able to achieve ultra low power with very high performance and
functionality, all in one of the smallest footprints available. Target
markets include media players, navigation devices, smart phones,
tablets, medical equipment, exercise equipment, consumer audio
equipment, etc. Features such as capless headphone design and an
internal PLL help lower overall system cost.
AUDIO CODEC
Features
Analog Inputs
• Stereo LINEIN - Support for external analog input
• Stereo LINEIN - Codec bypass for low power
• MIC bias provided
• Programmable MIC gain
• ADC - 85 dB SNR (-60 dB input) and -73 dB THD+N
(VDDA = 1.8 V)
Analog Outputs
• HP Output - Capless design
• HP Output - 62.5 mW max, 1.02 kHz sine into 16 load at 3.3 V
• HP Output - 100 dB SNR (-60 dB input) and -80 dB THD+N
(VDDA = 1.8 V, 16 load, DAC to headphone)
• LINEOUT - 100 dB SNR (-60 dB input) and -85 dB THD+N
(VDDIO = 3.3 V)
Digital I/O
• I2S port to allow routing to Application Processor
Integrated Digital Processing
• Freescale surround, Freescale bass, tone control/ parametric
equalizer/graphic equalizer clocking/control
• PLL allows input of an 8.0 MHz to 27 MHz system clock - standard
audio clocks are derived from PLL
Power Supplies
• Designed to operate from 1.62 to 3.6 volts
PB-FREE
98ARE10742D
20-PIN QFN
PB-FREE
98ARE10739D
32-PIN QFN
ORDERING INFORMATION
Device
Temperature
Range (TA)
SGTL5000XNLA3/R2
-40 to 85 °C
SGTL5000XNAA3/R2
Package
20 QFN
32 QFN
MP3/FM Input
MIC IN/Speech
Recognition
Application
Processor
LINEIN_R
LINEIN_L
MIC_IN
MIC_BIAS
I2S_DIN
I2S_LRCLK
I2S_SCLK
I2S_DOUT
Analog In
(Stereo
Line In,
MIC)
I2S
Interface
SYS_MCLK
PLL
ADC
Audio
Switch
DAC
Headphone /
Line Out
w/ volume
Audio
Processing
HP_R
HP_L
LINEOUT_R
LINEOUT_L
I2C/SPI Control
Note: SPI is not supported in the 3.0 mm x 3.0 mm 20-pin QFN package
Figure 1. SGTL5000 Simplified Application Diagram
Headphone
Speaker
Amp/Docking
Station/FMTX
Freescale Semiconductor, Inc. reserves the right to change the detail specifications,
as may be required, to permit improvements in the design of its products.
© Freescale Semiconductor, Inc., 2008-2013. All rights reserved.

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SGTL5000 pdf
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings
Exceeding the absolute maximum ratings shown in the following table could cause permanent damage to the part and is not
recommended. Normal operation is not guaranteed at the absolute maximum ratings, and extended exposure could affect long
term reliability.
Ratings
Symbol
Value
Unit
ELECTRICAL RATINGS
Maximum Digital Voltage
Maximum Digital I/O Voltage
Maximum Analog Supply Voltage
Maximum voltage on any digital input
Maximum voltage on any analog input
THERMAL RATINGS
VDDD
VDDIO
VDDA
1.98
3.6
3.6
GND-0.3 to VDDIO+0.3
GND-0.3 to VDDA+0.3
V
V
V
V
V
Storage Temperature
Operating Temperature
Ambient
TSTG
TA
- 55 to 125
-40 to 85
C
C
Table 3. Recommended Operating Conditions
Ratings
Symbol
Value
Unit
Digital Voltage (If supplied externally). External VDDD connection required for
new designs.
VDDD
1.1 to 2.0
V
Digital I/O Voltage
Analog Supply Voltage
VDDIO
VDDA
1.62 to 3.6
1.62 to 3.6
V
V
Analog Integrated Circuit Device Data
Freescale Semiconductor
SGTL5000
5

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SGTL5000 arduino
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
.
Ti2s_s
1/Fsclk
I2S_SCLK
I2S_LRCLK
In slave mode
I2S_LRCLK
In master mode
Ti2s_d
I2S_SCLK
Ti2s_s
Ti2s_h
I2S_DIN
I2S_DOUT
Ti2s_d
1/Flrclk
I2S_LRCLK
Figure 7. I2S Interface Timing
Analog Integrated Circuit Device Data
Freescale Semiconductor
SGTL5000
11

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