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CH8438 데이터시트 PDF




Chrontel에서 제조한 전자 부품 CH8438은 전자 산업 및 응용 분야에서
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부품번호 CH8438 기능
기능 Video Multiplexer
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CH8438 데이터시트, 핀배열, 회로
CHRONTEL
Video Multiplexer with Source Control
CH8438
Preliminary
Features
• Triple 8-bit DAC and buffers support 1280 x 1024
display resolution
• High-speed multiplexing between digital
and analog RGB signals
• 24-bit digital RGB interface supports up to
16.7 million colors
• Supports CCIR601 4:2:2 YCrCb input formats
• Built in YUV-to-RGB color space conversion
• Analog auxiliary inputs with programmable
input attenuation
• 2’s complement input capability on Red and Blue
channels, supporting 4:4:4 YUV format with analog
YUV outputs
• Programmable brightness, contrast, and hue
attributes for the digital input signals
• Programmable switching delay
• Two-wire serial programming
• Enhanced replacement of STV8438
• CMOS technology in 44-pin PQFP
• 5V supply
Description
Chrontel’s CH8438 combines a 24-bit digital video
interface, YUV to RGB converter, three 8-bit DACs, a
high-speed analog multiplexer, an analog input
attenuator, and three video buffers in one integrated
circuit.
The CH8438’s high-speed analog multiplexer allows
simultaneous display of video (digital RGB) with
graphics (analog RGB), making CH8438 ideal for
video games, editing, PC video, and for applications
requiring picture-in-picture capability.
CH8438 provides a 24-bit digital pixel bus interface,
which supports RGB, 4:4:4 YUV and 4:2:2 YCrCb
input formats. With the 4:2:2 YCrCb input format, a
built-in color space converter translates YUV video
information to RGB before muxing with the analog
graphics input, while the 4:4:4 YUV format accepts 2’s
complement Red and Blue data, and provides analog
YUV outputs.
CH8438 has seven 4-bit control registers which are
programmable with the serial interface pins. The
programmable functions include digital input formats;
video attributes of contrast, hue, and brightness; analog
input attenuation; and switching delay.
RAUX
GAUX
BAUX
CLK
DVDD
AVDD
0
ROUT
P[23:0]
24
0
GOUT
0
BOUT
R/C
SD
SC
COM
Rev. 1.0, 8/28/97
SERIAL I/F
12 2 3
3
8-TAP DELAY LINE
DGND
AGND
Figure 1: CH8438 Block Diagram
1




CH8438 pdf, 반도체, 판매, 대치품
Preliminary
CH8438
4(a) Auxiliary Analog Input with blank pedestal
Y1
Y2 = PEDESTAL
WHITE LEVEL
BLACK LEVEL
BLANK LEVEL
4(b) Analog Output
Y1' = Y1 x Attenuation
Y2' = Y2 x Attenuation
WHITE LEVEL
BLACK LEVEL
BLANK LEVEL
Figure 4: Analog Input and Output Waveforms (with blank pedestal)
Rev. 1.0, 8/28/97
7

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CH8438 전자부품, 판매, 대치품
Preliminary
Register Descriptions (continued)
CH8438
R2: Red or V Digital Input Gain Control Register
D3 D2 D1
RV_G3
RV_G2
RV_G1
The initial value of this register upon power-up is 1000
RV_G[3:0] = Digital Input Gain
D0
RV_G0
Mode 0: These bits select the gain applied to the digital red input
Modes
1, 2, 3, 4, 5: These bits select the gain applied to the digital V inputs
For detailed information, please refer to Table 9 on page 15.
R3: Green or Y Digital Input Gain Control Register
D3 D2 D1
GY_G3
GY_G2
GY_G1
The initial value of this register upon power-up is 1000
GY_G[3:0] = Digital Input Gain
D0
GY_G0
Mode 0: These bits select the gain applied to the digital green input
Modes
1, 2, 3, 4, 5: These bits select the gain applied to the digital Y inputs
For detailed information, please refer to Table 9 on page 15.
R4: Blue or U Digital Input Gain Control Register
D3 D2 D1
BU_G3
BU_G2
BU_G1
The initial value of this register upon power-up is 1000
BU_G[3:0] = Digital Input Gain
D0
BU_G0
R2, R3, and R4
Mode 0: These bits select the gain applied to the digital blue input
Modes
1, 2, 3, 4, 5: These bits select the gain applied to the digital U inputs
For detailed information, please refer to Table 9 on page 15.
Rev. 1.0, 8/28/97
13

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CH8438

Video Multiplexer

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