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FAN54041 데이터시트 PDF




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부품번호 FAN54041 기능
기능 Li-Ion Switching Charger
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FAN54041 데이터시트, 핀배열, 회로
July 2013
FAN54040 FAN54047
USB-OTG, 1.55 A, Li-Ion Switching Charger with Power
Path and 2.3 A Production Test Support
Features
Fully Integrated, High-Efficiency Charger for Single-Cell
Li-Ion and Li-Polymer Battery Packs
Power Path Circuit Ensures Fast System Startup with a
Dead Battery when VBUS is Connected
1.55 A Maximum Charge Current
Float Voltage Accuracy:
- 0.5% at 25°C
- 1% from 0 to 125°C
5% Input and Charge Current Regulation Accuracy
Temperature-Sense Input Prevents Auto-Charging for
JEITA Compliance
Thermal Regulation and Shutdown
4.2 V at 2.3 A Production Test Mode
5 V, 500 mA Boost Mode for USB OTG
28 V Absolute Maximum Input Voltage
6 V Maximum Input Operating Voltage
Programmable through High-Speed I2C Interface
(3.4 Mb/s) with Fast Mode Plus Compatibility
- Input Current
- Fast-Charge / Termination Current
- Float Voltage
- Termination Enable
3 MHz Synchronous Buck PWM Controller with
Wide Duty Cycle Range
Small Footprint 1 H External Inductor
Safety Timer with Reset Control
Dynamic Input Voltage Control
Very Low Battery Current when Charger Inactive
Applications
Cell Phones, Smart Phones, PDAs
Tablet, Portable Media Players
Gaming Device, Digital Cameras
All trademarks are the property of their respective owners.
© 2012 Fairchild Semiconductor Corporation
FAN54040 – FAN54047 • Rev. 1.0.2
Description
The FAN5404X family includes I2C controlled 1.55 A USB-
compliant switch-mode chargers with power path operation
and USB OTG boost operation. Integrated with the charger,
the IC supports production test mode, which provides 4.2 V
at up to 2.3 A to the system.
To facilitate fast system startup, the IC includes a power
path circuit, which disconnects the battery from the system
rail, ensuring that the system can power up quickly following
a VBUS connection. The power path circuit ensures that the
system rail stays up when the charger is plugged in, even if
the battery is dead or shorted.
The charging parameters and operating modes are
programmable through an I2C Interface that operates up to
3.4 Mbps. The charger and boost regulator circuits switch at
3 MHz to minimize the size of external passive components.
The FAN5404X provides battery charging in three phases:
conditioning, constant current, and constant voltage. The
integrated circuit automatically restarts the charge cycle
when the battery falls below a voltage threshold. If the input
source is removed, the IC enters a high-impedance mode
blocking battery current from leaking to the input. Charge
status is reported back to the host through the I2C port.
Dynamic input voltage control prevents a weak adapters
voltage from collapsing, ensuring charging capability from
such adapters.
The FAN5404X is available in a 25-bump, 0.4 mm pitch,
WLCSP package.
VBUS
CBUS
PGND
PMID
CMID
POK_B
ILIM
SDA
SCL
DIS
STAT
AGND
FAN5404X
SW
SYS
L1
CSYS
Q5
GATE
External
PMOS
VBAT
NTC
REF RREF
CREF
T
SYSTEM
LOAD
CBAT
BATTERY
+
Figure 1. Typical Application
www.fairchildsemi.com




FAN54041 pdf, 반도체, 판매, 대치품
Pin Configuration
SDA PGND SW PMID VBUS
A1 A2 A3 A4 A5
SCL
B1 B2 B3 B4 B5
DIS GATE
C1 C2 C3 C4 C5
STAT
D1
D2
SYS VBAT NTC
D3 D4 D5
POK_B AGND
E1 E2 E3
REF
E4 E5
Figure 3. Top View
A5 A4 A3 A2 A1
B5 B4 B3 B2 B1
C5 C4 C3 C2 C1
D5 D4 D3 D2 D1
E5 E4 E3 E2 E1
Figure 4. Bottom View
Pin Definitions
Pin #
A1
B1
C1
D1
E1
E1
A2 D2
E2
A3 C3
D3 E3
A4 C4
D4 E4
A5 B5
C5
D5
E5
Name
SDA
SCL
Description
I2C Interface Serial Data. This pin should not be left floating.
I2C Interface Serial Clock. This pin should not be left floating.
DIS
Disable. If this pin is held HIGH, Q1 and Q3 are turned off, creating a HIGH Z condition at VBUS and
the PWM converter is disabled.
STAT
Status. Open-drain output indicating charge status. The IC pulls this pin LOW when charge is in
progress; can be used to signal the host processor when a fault condition occurs.
Power OK (FAN54040-2). Open-drain output that pulls LOW when VBUS is plugged in and the battery
POK_B has risen above VLOWV. This signal is used to signal the host processor that it can begin to draw
significant current.
ILIM
PGND
AGND
Input Current Limit (FAN54045-7). Controls input current limit in Auto-Charge Mode. When LOW, input
current is limited to 100 mA maximum. When HIGH, input current is limited to 500 mA. In 32-Second
Mode, the input current limit is set by the IBUSLIM bits.
Power Ground. Power return for gate drive and power transistors. The connection from this pin to the
bottom of CMID should be as short as possible.
Analog Ground. All IC signals are referenced to this node.
SW Switching Node. Connect to output inductor.
SYS
System Supply. Output voltage of the switching charger and input to the power path controller. Bypass
SYS to PGND with a 10 μF capacitor.
PMID
Power Input Voltage. Power input to the charger regulator, bypass point for the input current sense.
Bypass with a minimum of a 4.7 F, 6.3 V capacitor to PGND.
VBAT
Battery Voltage. Connect to the positive (+) terminal of the battery pack. Bypass with a 10 F capacitor
to PGND. VBAT is a power path connection.
VBUS Charger Input Voltage and USB-OTG output voltage. Bypass with a 1 F capacitor to PGND.
GATE
External MOSFET Gate. This pin controls the gate of an external P-channel MOSFET transistor used to
augment the internal ideal diode. The source of the P-channel MOSFET should be connected to SYS
and the drain should be connected to VBAT.
NTC
Thermistor input. The IC compares this node with taps on a resistor divider from REF to inhibit auto-
charging when the battery temperature is outside of permitted fast-charge limits.
REF Reference Voltage. REF is a 1.8 V regulated output.
© 2012 Fairchild Semiconductor Corporation
FAN54040 FAN54047 Rev. 1.0.2
4
www.fairchildsemi.com

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FAN54041 전자부품, 판매, 대치품
Electrical Specifications (Continued)
Unless otherwise specified: according to the circuit of Figure 1; recommended operating temperature range for TJ and TA;
VBUS=5.0 V; HZ_MODE; OPA_MODE=0; (Charge Mode); SCL, SDA=0 or 1.8 V; and typical values are for TJ=25°C.
Symbol
Parameter
Conditions
Min. Typ. Max. Unit
Input Power Source Detection
T1 T1 (0°C) Temperature Threshold
T2 T1 (10°C) Temperature Threshold
T3 T1 (45°C) Temperature Threshold
T4 T1 (60°C) Temperature Threshold
Input Power Source Detection
VIN(MIN)1 VBUS Input Voltage Rising
VIN(MIN)2 Minimum VBUS during Charge
tVBUS_VALID VBUS Validation Time
VBUS Control Loop
VBUSLIM VBUS Loop Setpoint Accuracy
Input Current Limit
IBUSLIM
Charger Input Current Limit
Threshold
VREF Bias Generator
VREF
Bias Regulator Voltage
Short-Circuit Current Limit
Battery Recharge Threshold
VRCH
Recharge Threshold
Deglitch Time
STAT, POK_B Output
VSTAT(OL) STAT Output Low
ISTAT(OH) STAT High Leakage Current
Battery Detection
IDETECT
Battery Detection Current before
Charge Done (Sink Current)(5)
tDETECT Battery Detection Time
Sleep Comparator
VSLP
Sleep-Mode Entry Threshold,
VBUS VBAT
Power Switches (see Figure 2)
Q3 On Resistance (VBUS to PMID)
RDS(ON)
Q1 On Resistance (PMID to SW)
Q2 On Resistance (SW to GND)
Q4 On Resistance (SYS to VBAT)
ISYNC
Synchronous to Non-Synchronous
Current Cut-Off Threshold(6)
To Initiate and Pass VBUS Validation
During Charging
IBUSLIM Set to 100 mA
IBUSLIM Set to 500 mA
VBUS > VIN(MIN)
Below V(OREG)
VBAT Falling Below VRCH Threshold
ISTAT=10 mA
VSTAT=5 V
Begins after Termination Detected
and VBAT < VOREG VRCH
2.3 V < VBAT < VOREG, VBUS Falling
IIN(LIMIT)=500 mA
VBAT=4.2 V
Low-Side MOSFET (Q2) Cycle-by-
Cycle Current Limit
71.9
62.6
31.9
21.3
3
88
450
100
0
73.9
64.6
32.9
23.3
4.29
3.71
30
93
475
1.8
2.5
120
130
0.8
262
0.04
180
130
150
70
140
75.9
66.6
34.9
25.3
% of
VREF
4.42 V
3.94 V
ms
+3 %
98
mA
500
V
mA
150 mV
ms
0.4 V
1 A
mA
ms
0.10 V
250
225 mΩ
225
100 mΩ
mA
Continued on the following page…
© 2012 Fairchild Semiconductor Corporation
FAN54040 FAN54047 Rev. 1.0.2
7
www.fairchildsemi.com

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