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부품번호 | DM74S112 기능 |
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기능 | Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop | ||
제조업체 | Fairchild Semiconductor | ||
로고 | |||
전체 4 페이지수
August 1986
Revised April 2000
DM74S112
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop
with Preset, Clear, and Complementary Outputs
General Description
This device contains two independent negative-edge-trig-
gered J-K flip-flops with complementary outputs. The J and
K data is processed by the flip-flops on the falling edge of
the clock pulse. The clock triggering occurs at a voltage
level and is not directly related to the transition time of the
negative going edge of the clock pulse. Data on the J and
K inputs can be changed while the clock is HIGH or LOW
without affecting the outputs as long as setup and hold
times are not violated. A low logic level on the preset or
clear inputs will set or reset the outputs regardless of the
logic levels of the other inputs.
Ordering Code:
Order Number Package Number
Package Description
DM74S112
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Connection Diagram
Function Table
Inputs
Outputs
PR CLR CLK J K
Q
Q
L H X XX H
L
HL
X XX L
H
LL
X X X H*
H*
HH
HH
HH
HH
↓
LL
Q0
↓ HL H
Q0
L
↓ LH L
H
↓ HH
Toggle
HH
H X X Q0
Q0
H = HIGH Logic Level
X = Either LOW or HIGH Logic Level
L = LOW Logic Level
↓ = Negative going edge of pulse.
Q0 = The output logic level of Q before the indicated input conditions were
established.
* = This configuration is nonstable; that is, it will not persist when either the
preset and/or clear inputs return to its inactive (HIGH) level.
Toggle = Each output changes to the complement of its previous level on
each falling edge of the clock pulse.
© 2000 Fairchild Semiconductor Corporation DS006459
www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
www.fairchildsemi.com
4
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구 성 | 총 4 페이지수 | ||
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구매 문의 | 일반 IC 문의 : 샘플 및 소량 구매 ----------------------------------------------------------------------- IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한 광범위한 전력 반도체를 판매합니다. 전력 반도체 전문업체 상호 : 아이지 인터내셔날 사이트 방문 : [ 홈페이지 ] [ 블로그 1 ] [ 블로그 2 ] |
부품번호 | 상세설명 및 기능 | 제조사 |
DM74S11 | Triple 3-Input AND Gate | Fairchild Semiconductor |
DM74S112 | Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop | Fairchild Semiconductor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |