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AR2317 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 AR2317
기능 Single Chip MAC/Baseband/Radio and Processor
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AR2317 데이터시트, 핀배열, 회로
Data Sheet
PRELIMINARY
April 2006
AR2317 Single Chip MAC/Baseband/Radio and Processor
for 2.4 GHz Wireless LANs
General Description
Features
The Atheros AR2317 is an all-CMOS, fully-
Integrated high-output PA
integrated, single-chip 802.11b/g WLAN
Integrated LNA/optional external LNA
solution. It integrates the PA, LNA, 2.4GHz
support
radio, baseband PHY, MAC, and a MIPS 4000
Integrated 1.8 V voltage regulator; NO need
CPU into a single chip for wireless access point
for a 1.8 V supply
and router applications. Other major modules
Switched Rx antenna diversity
include 802.3 Ethernet MAC and MII interface,
Integrated Rx/Tx antenna switch
SDRAM controller, external memory interface
Integrated power detector
for Flash, ROM, or RAM, a UART, GPIOs as
25 MHz output for Ethernet switch
well as LED controls.
The AR2317 implements an 802.11 MAC/BB
processor supporting all IEEE 802.11g data
rates (1 to 54 Mbps) and all IEEE 802.11b
Ycomplementary key coding (CCK) data rates
(1 to 11 Mbps). Additional features include
Pforward error correction coding at rates for 1/
2, 2/3, and 3/4, signal detection, automatic
Ogain control, frequency offset estimation,
symbol timing, channel estimation, error
Crecovery, enhanced security, and quality of
service (QoS). The AR2317 performs receive
Tand transmit filtering for IEEE 802.3 and 802.11
networks.
DO NOSystem Block Diagram
Integrated MIPS 4000 processor
180 MHz processor frequency
IEEE 802.11b/g Access Point, Ad Hoc, and
station functions supported
OFDM and CCK modulation schemes
supported
Data rates of 1, 2, 5.5, 6, 9, 11, 12, 18, 24, 36,
48, 54 Mbps
IEEE 802.3 Ethernet MAC supporting 10/
100 Mbps, full and half duplex, and MII
interface to external Ethernet PHY
UART for console support
IEEE 1149.1 standard test access port and
boundary scan architecture supported
EJTAG based debugging of the processor
core supported
Standard 0.18 μm CMOS technology
12 mm x 12 mm 260 BGA package
Flash SDRAM Interface
LNA
LNA
RF
Switch
PA
AR2317
Receiver
Frequency
Synthesizer
Transmitter
Bias/
Control
SDRAM
Controller
and Memory
Interface
MIPS
Processor
Baseband
(PHY) and
Wireless MAC
Ethernet
MAC
Fast UART
Peripheral
Interface
MII Interface
40 MHz
Crystal
Serial Interface
LED Controls
GPIOs
© 2000-2006 by Atheros Communications, Inc. All rights reserved. Atheros™, 5-UP™, Driving the Wireless Future™, Atheros Driven™, Atheros Turbo
Mode™, and the Air is Cleaner at 5-GHz™ are trademarks of Atheros Communications, Inc. The Atheros logo is a registered trademark of
Atheros Communications, Inc. All other trademarks are the property of their respective holders.
Subject to change without notice.
COMPANY CONFIDENTIAL
1




AR2317 pdf, 반도체, 판매, 대치품
PRELIMINARY
3.2.2 SSDR-DRAM Timing Register 0
(MEMCTL_STMG0R) 32
3.2.3 SDR-DRAM Timing Register 1
(MEMCTL_STMG1R) 32
3.2.4 SDR-DRAM Control Register
(MEMCTL_SCTLR) 33
3.2.5 SDR-DRAM Refresh Interval
Register (MEMCTL_SREFR) 33
3.3 UART Registers 34
3.3.1 Receive Buffer Register
(UART_RBR); Transmit Holding
Register (UART_THR); Divisor
Latch Low Register
(UART_DLL) 34
3.3.2 Interrupt Enable Register
(UART_IER); Divisor Latch High
(UART_DLH) 34
3.3.3 Interrupt Identity Register
(UART_IIR); FIFO Control Regis-
ter (UART_FCR) 35
3.3.4 Line Control Register
(UART_LCR) 35
3.3.5 Modem Control Register
(UART_MCR) 36
3.3.6 Line Status Register
(UART_LSR) 36
T3.3.7 Modem Status Register
O(UART_MSR) 37
3.3.8 Scratch Register
N(UART_SCR) 37
3.4 SPI Flash Interface Registers 38
O3.4.1 SPI Control/Status (SPI_CS)
3.4.2 SPI Address/Opcode
D(SPI_AO) 39
38
3.4.3 SPI Data (SPI_D) 39
3.4.4 SPI Register Notes 39
4 Package Dimensions 41
5 Ordering Information 43
COPY
4 • AR2317 MAC/BB/Radio and Processor for 2.4 GHz WLANs
4 April 2006
Atheros Communications, Inc.
COMPANY CONFIDENTIAL

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AR2317 전자부품, 판매, 대치품
Table 1-2. AR2317 Pin Assignments (12–22)
12 13 14 15 16 17 18 19 20
A RFANT1P
RFANT1P
RFANT1N RFANT1N
PABIAS
AVDD33 RFANT2N RFANT2P AVDD33
B PABIAS
PABIAS
PABIAS
PABIAS
PABIAS
AVDD33
GND ALDO_PWD GND
C NA NA NA NA NA NA NA NA NA
D NA NA NA NA NA NA NA NA NA
NA NA NA NA NA NA NA NA NA
E
F NA NA NA NA NA NA NA NA NA
G GND
GND
GND
GND
GND
NA
NA
NA NA
H GND
GND
GND
GND
GND
NA
NA
NA NA
J GND
GND
GND
GND
GND
NA
NA
NA NA
K GND
GND
GND
GND
GND
NA
NA
NA NA
L GND
GND
GND
GND
GND
NA
NA
NA NA
M GND
GND
GND
GND
GND
NA
NA
NA NA
N GND
GND
GND
GND
GND
NA
NA
NA NA
P GND
GND
GND
GND
GND
NA
NA
NA NA
R GND
GND
GND
GND
GND
NA
NA
NA NA
T GND
GND
GND
GND
GND
NA
NA
NA NA
U NA NA NA NA NA NA NA NA NA
V NA NA NA NA NA NA NA NA NA
W NA NA NA NA NA NA NA NA NA
Y NA NA NA NA NA NA NA NA NA
AA ETH_COL
ETH_MDC ETH_MDIO ETH_TXC ETH_CRS ETH_RXD_2 ETH_TXEN ETH_TXD_2 GND
ETH_RXERR ETH_RESET_L ETH_RXC ETH_RXDV ETH_RXD_0 ETH_RXD_1 ETH_RXD_3 ETH_TXD_3 VDD18_
AB BYPASS
21
GND
GND
ATBN
ALDO_SEL1
AVDD33
AVDD33
AVDD33
RES
RES
RES
AVDD33
UART_SOUT
TCLK
TDO
TRST_L
EJTAG_SEL
SPI_CK
SPI_CS_L
ETH_TXD_0
GND
GND
GND
22
GND
GND
NC
ALDO_SEL0
RXVDD_
BYPASS
AVDD_BYPASS
AVDD33
RES
BIASREF
XTALI
XTALO
UART_SIN
TMS
TDI
GPIO_6
COLD_RST_L
VDD33
SPI_MOSI
SPI_MISO
ETH_TXD_1
GND
GND

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