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PDF GTL1655DGG Data sheet ( Hoja de datos )
| Número de pieza | GTL1655DGG | |
| Descripción | 16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion | |
| Fabricantes | NXP Semiconductors | |
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GTL1655
16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion
Rev. 01 — 11 May 2004
Product data
1. Description
The GTL1655 is a 16-bit bus transceiver that incorporates HIGH-drive
LOW-output-impedance (100 mA/12 Ω) with LVTTL-to-GTL/GTL+ and
GTL/GTL+-to-LVTTL logic level translation.
The device is configured as two 8-bit transceivers that share a common clock and a
master output enable pin, but also have individual latch timing and output enable
signals. D-type flip-flops and D-type latches enable three modes of data transfer;
Clocked, Latched, or Transparent. The GTL1655 provides the ideal interface between
cards operating at LVTTL levels and backplanes using GTL/GTL+ signal levels. The
combination of reduced output swing, reduced input threshold levels and configurable
edge control provides the higher speed operation of GTL/GTL+ backplanes.
The GTL1655 can be used at GTL (VTT = 1.2 V, VREF = 0.8 V) or GTL+ (VTT = 1.5 V,
VREF = 1.0 V) signalling levels. Port A and the control inputs are compliant with
LVTTL signal levels and are 5 V tolerant. Port B is designed to operate at GTL or
GTL+ signal levels, with VREF providing the reference voltage input.
The latch enable pins (nLEAB and nLEBA), the output enable pins (nOEAB, nOEBA)
and the clock pin (CP) are used to control the data flow through the two 8-bit
transceivers (n = 1 or 2). When nLEAB is set HIGH, the device will operate in the
transparent mode Port A to Port B. HIGH-to-LOW transitions of nLEAB will latch A
data independently of CP HIGH or LOW (latched mode). LOW-to-HIGH transitions of
CP will clock A data to the B port if nLEAB is LOW (clocked mode). Using the control
pins nLEBA, nOEBA and CP in the same way, data flow from Port B to Port A can be
controlled. The OE pin can be used to disable all of the I/O pins.
To optimize signal integrity, the GTL1655 features an adjustable edge rate control
(VERC). By adjusting VERC between GND and VCC, a designer can adjust the Port B
edge rate to suit an application’s load conditions.
The GTL1655 permits true live insertion capability by incorporating:
• BIAS VCC, to pre-charge outputs and avoid disturbing active data during card
insertion.
• Ioff to disable current flow through powered-off I/Os.
• Power-up 3-state, which ensures outputs are high-impedance during power-up,
thus preventing bus contention issues. Once VCC is above 1.5 V, the power-up
3-state circuit relinquishes control of the outputs to the OE pin. To ensure the
outputs remain 3-state, the OE pin should be tied to VCC via a pull-up resistor.
1 page  
Philips Semiconductors
GTL1655
16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion
5.2 Pin description
Table 4: Pin description
Symbol
Pin
Description
1OEAB
1
output enable 1A-to-1B (active-LOW)
1OEBA
2
output enable 1B-to-1A (active-LOW)
VCC
1A1 to 1A8
3, 15, 28, 50
DC supply voltage
4, 6, 7, 9, 11, 13, data inputs/outputs port 1A
14, 16
GND
5, 8, 10, 12, 18,
21, 24, 26, 30,
39, 44, 47, 53,
57, 60
ground (0 V)
2A1 to 2A8
17, 19, 20, 22, data inputs/outputs port 2A
23, 25, 27, 29
2OEAB
31
output enable 2A-to-2B (active-LOW)
2OEBA
32
output enable 2B-to-2A (active-LOW)
OE 33
output enable, all I/O pins (active-LOW)
2LEBA
34
latch enable 2B-to-2A
2LEAB
35
latch enable 2A-to-2B
BIAS_VCC
2B8 to 2B1
36
37, 38, 40, 42,
43, 45, 46, 48
bias supply voltage
data inputs/outputs port 2B
VREF
1B8 to 1B1
41
49, 51, 52, 54,
55, 56, 58, 59
reference voltage
data inputs/outputs port 1B
VERC
1LEBA
61
62
edge-rate control voltage Port B
latch enable 2B-to-2A
1LEAB
63
latch enable 1A-to-1B
CP 64
clock input
9397 750 12936
Product data
Rev. 01 — 11 May 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
5 of 23
5 Page 
Philips Semiconductors
GTL1655
16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion
Table 10: DC characteristics…continued
Tamb = −40 °C to +85 °C; values otherwise stated VREF = 1 V; VTT = 1.5 V.
Symbol Parameter
Conditions
ICC quiescent supply
current
outputs
HIGH
VCC = 3.6 V;
Vi = VCC or GND;
Io = 0 mA
outputs
LOW
VCC = 3.6 V;
Vi = VCC or GND;
Io = 0 mA
∆ICC
Ci
additional quiescent
supply current per input
pin; except port B
input capacitance
disabled
VCC = 3.6 V;
Vi = VCC or GND;
Io = 0 mA
VCC = 3.6 V; one input at
VCC − 0.6 V; port A or control inputs
at VCC or GN D
control pins VCC = 3.6 V;
Vi = VCC or 0
[4]
CIO I/O capacitance
port A
port B
VCC = 3.6 V;
Vi = VCC or 0
VCC = 3.6 V;
Vi = VCC or 0
Min
-
-
-
-
-
-
-
Typ[1]
-
Max
45
- 45
- 45
0.1 -
35
78
8 10
Unit
mA
mA
mA
mA
pF
pF
pF
[1] All typical values are measured at VCC = 3.3 V and Tamb = 25 °C.
[2] This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to
another.
[3] For I/O ports, this parameter IOZ includes the input leakage current.
[4] This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
Table 11: Live insertion characteristics
Tamb = −40 °C to +85 °C
Symbol
Parameter
Conditions
ICC supply current
(BIAS VCC)
Vo output voltage
Io output current
VCC = 0 V to 3.0 V; V (port B) = 0 to 1.2 V;
Vi (BIAS VCC) = 3.0 V to 3.6 V
VCC = 3.0 V to 3.6 V;
V (port B) = 0 to 1.2 V;
Vi (BIAS VCC) = 3.0 V to 3.6 V
port B
VCC = 0 V;
Vi (BIAS VCC) = 3.3 V
port B
VCC = 0 V; V (port B) = 0.4 V;
Vi (BIAS VCC) = 3 V to 3.6 V
VCC = 0 V to 3.6 V; OE = 3.3 V;
V (port B) = 0 V to 1.5 V
VCC = 0 V to 1.5 V;
OE = 0 V to 3.3 V;
V (port B) = 0 V to 1.5 V
Min Typ Max Unit
- - 5 mA
- - 10 µA
1-
−1 -
--
--
1.2 V
- µA
300 µA
300 µA
9397 750 12936
Product data
Rev. 01 — 11 May 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
11 of 23
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