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GTLP16616MEA 데이터시트 PDF




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부품번호 GTLP16616MEA 기능
기능 17-Bit TTL/GTLP Bus Transceiver with Buffered Clock
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GTLP16616MEA 데이터시트, 핀배열, 회로
June 1997
Revised October 1998
GTLP16616
17-Bit TTL/GTLP Bus Transceiver
with Buffered Clock
General Description
The GTLP16616 is a 17-bit registered bus transceiver that
provides TTL to GTLP signal level translation. It allows for
transparent, latched and clocked modes of data flow and
provides a buffered GTLP (CLKOUT) clock output from the
TTL CLKAB. The device provides a high speed interface
between cards operating at TTL logic levels and a back-
plane operating at GTLP logic levels. High speed back-
plane operation is a direct result of GTLP’s reduced output
swing (<1V), reduced input threshold levels and output
edge rate control. The edge rate control minimizes bus set-
tling time. GTLP is a Fairchild Semiconductor derivative of
the Gunning Transceiver logic (GTL) JEDEC standard
JESD8-3.
Fairchild’s GTLP has internal edge-rate control and is pro-
cess, voltage, and temperature (PVT) compensated. Its
function is similar to BTL and GTL but with different output
levels and receiver threshold. GTLP output LOW level is
typically less than 0.5V, the output level HIGH is 1.5V and
the receiver threshold is 1.0V.
Features
s Bidirectional interface between GTLP and TTL logic
levels
s Edge Rate Control to minimize noise on the GTLP port
s Power up/down/off high impedance for live insertion
s External VREF pin for receiver threshold
s CMOS technology for low power dissipation
s 5 V tolerant inputs and outputs on the A-Port
s Bus-hold data inputs on the A-Port eliminates the need
for external pull-up resistors on unused inputs.
s TTL compatible driver and control inputs
s Flow through pinout optimizes PCB layout
s Open drain on GTLP to support wired-or connection
s A-port source/sink 32 mA/+32 mA
s D-type flip-flop, latch and transparent data paths
s GTLP Buffered CLKAB signal available (CLKOUT)
s Recommended Operating Temperature 40°C to 85°C
Ordering Code:
Order Number Package Number
Package Description
GTLP16616MEA
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118 0.300” Wide
GTLP16616MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
© 1998 Fairchild Semiconductor Corporation DS500017.prf
www.fairchildsemi.com




GTLP16616MEA pdf, 반도체, 판매, 대치품
Absolute Maximum Ratings(Note 4)
Supply Voltage (VCC)
DC Input Voltage (VI)
DC Output Voltage (VO)
Outputs 3-STATE
Outputs Active (Note 5)
DC Output Sink Current into
A-Port IOL
DC Output Source Current from
A-Port IOH
DC Output Sink Current
into B-Port in the LOW State,
IOL
DC Input Diode Current (IIK)
VI < 0V
DC Output Diode Current (IOK)
VO < 0V
VO > VCC
ESD Rating
Storage Temperature (TSTG)
0.5V to +7.0V
0.5V to +7.0V
0.5V to +7.0V
0.5V to VCC + 0.5V
64 mA
64 mA
80 mA
50 mA
50 mA
+50 mA
>2000V
65°C to +150°C
Recommended Operating
Conditions (Note 6)
Supply Voltage VCC
VCC
VCCQ
Bus Termination Voltage (VTT) GTLP
Input Voltage (VI)
on A-Port and Control Pins
3.15V to 3.45V
4.75V to 5.25V
1.35V to 1.65V
0.0V to 5.5V
HIGH Level Output Current (IOH)
A-Port
32 mA
LOW Level Output Current (IOL)
A-Port
+32 mA
B-Port
+34 mA
Operating Temperature (TA)
40°C to +85°C
Note 4: The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Note 5: IO Absolute Maximum Rating must be observed.
Note 6: Unused inputs must be held high or low.
www.fairchildsemi.com
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GTLP16616MEA 전자부품, 판매, 대치품
AC Electrical Characteristics
Over recommended range of supply voltage and operating free-air temperature, VREF = 1.0V (unless otherwise noted). CL = 30 pF for B-Port
and CL = 50 pF for A-Port.
Symbol
From
To
Min
Typ
Max
Unit
(Input)
(Output)
(Note 10)
tPLH
A
B 1.0 4.3 6.5 ns
tPHL 1.0 5.0 8.2
tPLH
LEAB
B 1.8 4.5 6.7 ns
tPHL 1.5 5.3 8.7
tPLH
CLKAB
B 1.8 4.6 6.7 ns
tPHL 1.5 5.4 8.7
tPLH
CLKAB
CLKOUT
3.0
6.2
10.0
ns
tPHL 3.0 5.7 10.0
tPLH
OEAB
B or CLKOUT
1.6 4.4 6.3 ns
tPHL 1.3 6.1 9.8
tSKEW
B (Note 11)
CLKOUT
0
2 ns
tRISE
Transition time, B outputs (20% to 80%)
2.6 ns
tFALL
Transition time, B outputs (20% to 80%)
2.6
tPLH
B
A 2.0 5.6 8.2 ns
tPHL 1.4 5.0 7.2
tPLH
LEBA
A 2.1 4.2 6.3 ns
tPHL 1.9 3.3 5.0
tPLH
CLKBA
A 2.3 4.4 6.8 ns
tPHL 2.1 3.5 5.2
tPLH
CLKOUT
CLKIN
3.0
6.0
10.0
ns
tPHL 3.0 6.4 10.0
tPZH, tPZL
OEBA
A or CLKIN
1.5 5.0 6.4 ns
tPHZ, tPLZ
1.4 3.9 8.0
Note 10: All typical values are at VCC = 3.3V, VCCQ = 5.0V, and TA = 25°C.
Note 11: Skew is defined as the absolute value of the difference between the actual propagation delays for the CLKOUT pin and any B output transition
when measured with reference to CLKAB. This guarantees the relationship between B output data and CLKOUT such that data is coincident or ahead of
CLKOUT. This specification is guaranteed but not tested.
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부품번호상세설명 및 기능제조사
GTLP16616MEA

17-Bit TTL/GTLP Bus Transceiver with Buffered Clock

Fairchild Semiconductor
Fairchild Semiconductor

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