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PDF GTLP16T1655 Data sheet ( Hoja de datos )
| Número de pieza | GTLP16T1655 | |
| Descripción | 16-Bit LVTTL/GTLP Universal Bus Transceiver | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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August 1998
Revised April 2000
GTLP16T1655
16-Bit LVTTL/GTLP Universal Bus Transceiver
General Description
The GTLP16T1655 is a 16-bit universal bus transceiver
that provides LVTTL to GTLP signal level translation. It
allows for transparent, latched and clocked modes of data
transfer. The device provides a high speed interface
between cards operating at LVTTL logic levels and a back-
plane operating at GTLP logic levels. High speed back-
plane operation is a direct result of GTLP’s reduced output
swing (<1V), reduced input threshold levels and output
edge rate control. The edge rate control minimizes bus set-
tling time. GTLP is a Fairchild Semiconductor derivative of
the Gunning Transceiver Logic (GTL) JEDEC standard
JESD8-3.
Fairchild’s GTLP has internal edge-rate control and is pro-
cess, voltage, and temperature (PVT) compensated. Its
function is similar to BTL and GTL but with different output
levels and receiver threshold. GTLP output LOW level is
typically less than 0.5V, the output level HIGH is 1.5V and
the receiver threshold is 1.0V.
Features
s Bidirectional interface between GTLP and LVTTL logic
levels
s Variable Edge Rate Control pin to select desired edge
rate on the GTLP backplane (VERC)
s Partitioned as two 8-Bit transceivers with individual latch
timing and output control but with a common clock.
s Power up/down high impedance for live insertion.
s External pin to pre-condition I/O capacitance to high
state
s Bus-hold data inputs on the A-Port eliminates the need
for external pull-up resistors on unused inputs
s LVTTL compatible driver and control inputs
s Flow through pinout optimizes PCB layout
s Open drain on GTLP to support wired-or connection
s A Port source/sink −24 mA/+24 mA
s B Port sink +100mA
s D-type flip-flop, latch and transparent data paths
s −40°C to 85°C Temperature capability
s Available in TSSOP
Ordering Code:
Order Number Package Number
Package Description
GTLP16T1655MTD
MTD64
64-Lead Thin Shrink Small Outline Package, JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2000 Fairchild Semiconductor Corporation DS500172
www.fairchildsemi.com
1 page  
DC Electrical Characteristics
Over Recommended Operating Free-Air Temperature Range, VREF = 1.0V (unless otherwise noted).
Symbol
Test Conditions
Min
Typ
(Note 7)
VIH B Port
Others
VREF +0.05
2.0
VIL B Port
Others
0.0
VREF
GTLP
0.74
1.0
VIK VCC = 3.0V
II = −18 mA
VOH
A Port
VCC = Min to Max (Note 8)
IOH = −100 µA
VCC −0.2
VCC = 3.0V
IOH = −12 mA
2.4
IOH = −24 mA
2.2
VOL
A Port
VCC = Min to Max (Note 8)
IOL = 100 µA
VCC = 3.0V
IOL = 12 mA
IOL = 24 mA
B Port
VCC = 3.0V
IOL = 40 mA
IOL = 80 mA
IOL = 100 mA
II
A Port
VCC = 3.6V
VI = VCC or 0V
Control Pins VCC = 3.6V
VI = VCC or 0V
B Port
VCC = 3.6V
VI = VTT or GND
IOFF
Except
VCC = 0
VI or VO = 0 to
VERC
VCC
II(hold)
A Port
VCC = 3.0V
VI = 0.8V
75
VI = 2.0V
−75
VCC = 3.6V
VI = 0 to VCC
IOZH
A Port
VCC = 3.6V
VO = VCC
B Port
VO = 1.5V
IOZL
A Port
VCC = 3.6V
VO = 0V
B Port
VO = 0.4V
IOZPU
A Port
VCC = 0 to 1.5V
VO = 0.5 to 3V
(Note 9)
OE = 0 or VCC
IOZPD
A Port
VCC = 1.5 to 0V
VO = 0.5 to 3V
(Note 9)
OE = 0 or VCC
ICC A or B Ports VCC = 3.6
Outputs HIGH
(vcc)
IO = 0
Outputs LOW
VI = VCC or GND
Outputs Disabled
∆ICC
A Port and VCC = 3.6V
One Input at
0
(Note 10) Control Pins A or Control
VCC–0.6
Inputs at VCC or GND
Ci Control Pins
VI = VCC or 0
5.8
A Port
VI = VCC or 0
8.0
B Port
VI = VCC or 0
8.3
Note 7: All typical values are at VCC = 3.3V, and TA = 25°C.
Note 8: For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions.
Note 9: This is specified by characterization but not tested.
Note 10: This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
Max
VTT
VREF −0.05
0.8
1.1
−1.2
0.20
0.40
0.50
0.20
0.40
0.50
±10
±10
±10
100
±500
10
10
−10
−10
±50
±50
55
55
55
1
7.0
9.5
9.9
Units
V
V
V
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
µA
µA
µA
mA
mA
pF
5 www.fairchildsemi.com
5 Page 
Extended Electrical Characteristics (GTL)
Over recommended ranges of supply voltage and operating free-air temperature VREF = 0.8V (unless otherwise noted).
CL = 30 pF for B Port and CL = 50 pF for A Port.
Symbol
From
(Input)
To
(Output)
Min
Typ
(Note 19)
Max
Unit
tOSLH (Note 20)
AB
0.4 1.0 ns
tOSHL (Note 20)
0.4 1.0 ns
tPV(HL) (Note 21) (Note 22)
AB
1.5 ns
tOSLH (Note 20)
CLKAB
B
0.3 0.9 ns
tOSHL (Note 20)
0.3 0.6 ns
tPV(HL) (Note 21) (Note 22)
CLKAB
B
1.2 ns
tOSLH (Note 20)
BA
0.3 1.0 ns
tOSHL (Note 20)
0.3 1.0 ns
tOST (Note 20)
BA
0.6 1.5 ns
tPV (Note 21)
BA
1.6 ns
tOSLH (Note 20)
CLKAB
A
0.3 0.6 ns
tOSHL (Note 20)
0.3 0.6 ns
tOST (Note 20)
CLKAB
A
0.5 1.0 ns
tPV (Note 21)
CLKAB
A
1.1 ns
Note 19: All typical values are at VCC = 3.3V, and TA = 25°C.
Note 20: tOSHL/tOSLH and tOST—Output to output skew is defined as the absolute value of the difference between the actual propagation delay for all outputs
within the same packaged device. The specifications are given for specific worst case VCC and temperature and apply to any outputs switching in the same
direction either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH) or in opposite directions both HL and LH (tOST). This parameter is guaranteed by design and
statistical process distribution. Actual skew values between the GTL outputs could vary on the backplane due to the loading and impedance seen by the
device.
Note 21: tPV—Part to part skew is defined as the absolute value of the difference between the actual propagation delay for all outputs from device to device.
The parameter is specified for a specific worst case VCC and temperature. This parameter is guaranteed by design and statistical process distribution. Actual
skew values between the GTL outputs could vary on the backplane due to the loading and impedance seen by the device.
Note 22: Due to the open drain structure on GTL outputs, tOST and tPV(LH) in the A-to-B direction are not specified. Skew on these paths is dependent on the
VTT and RT values on the backplane.
11 www.fairchildsemi.com
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet GTLP16T1655.PDF ] | |
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