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부품번호 | GTLP18T612 기능 |
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기능 | 18-Bit LVTTL/GTLP Universal Bus Transceiver | ||
제조업체 | Fairchild Semiconductor | ||
로고 | |||
전체 9 페이지수
May 1999
Revised September 1999
GTLP18T612
18-Bit LVTTL/GTLP Universal Bus Transceiver
General Description
The GTLP18T612 is an 18-bit universal bus transceiver
which provides LVTTL to GTLP signal level translation. It
allows for transparent, latched and clocked modes of data
transfer. The device provides a high speed interface for
cards operating at LVTTL logic levels and a backplane
operating at GTLP logic levels. High speed backplane
operation is a direct result of GTLP’s reduced output swing
(< 1V), reduced input threshold levels and output edge rate
control. The edge rate control minimizes bus settling time.
GTLP is a Fairchild Semiconductor derivative of the Gun-
ning Transistor logic (GTL) JEDEC standard JESD8-3.
Fairchild's GTLP has internal edge-rate control and is Pro-
cess, Voltage, and Temperature (PVT) compensated. Its
function is similar to BTL or GTL but with different output
levels and receiver thresholds. GTLP output LOW level is
less than 0.5V, the output HIGH is 1.5V and the receiver
threshold is 1.0V.
Features
s Bidirectional interface between GTLP and LVTTL logic
levels
s Edge Rate Control to minimize noise on the GTLP port
s Power up/down high impedance for live insertion
s External VREF pin for receiver threshold
s BiCMOS technology for low power dissipation
s Bushold data inputs on A Port eliminates the need for
external pull-up resistors for unused inputs
s LVTTL compatible Driver and Control inputs
s Flow-through architecture optimizes PCB layout
s Open drain on GTLP to support wired-or connection
s A-Port source/sink −24 mA/+24 mA
s B-Port sink capability +50 mA
s D-type flip-flop, latch and transparent data paths
Ordering Code:
Order Number Package Number
Package Description
GTLP18T612MEA
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
GTLP18T612MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
© 1999 Fairchild Semiconductor Corporation DS500169
www.fairchildsemi.com
Absolute Maximum Ratings(Note 4)
Supply Voltage (VCC)
DC Input Voltage (VI)
DC Output Voltage (VO)
Outputs 3-STATE
Outputs Active (Note 5)
DC Output Sink Current into
A Port IOL
DC Output Source Current from
A Port IOH
DC Output Sink Current into
B Port in the LOW State, IOL
DC Input Diode Current (IIK)
VI < 0V
DC Output Diode Current (IOK)
VO < 0V
VO > VCC
ESD Performance
Storage Temperature (TSTG)
−0.5V to +4.6V
−0.5V to +4.6V
−0.5V to +4.6V
−0.5V to VCC + 0.5V
48 mA
−48 mA
100 mA
−50 mA
−50 mA
+50 mA
>2000V
−65°C to +150°C
Recommended Operating
Conditions (Note 6)
Supply Voltage VCC/VCCQ
Bus Termination Voltage (VTT)
GTLP
3.15V to 3.45V
1.47V to 1.53V
VREF
Input Voltage (VI)
on A Port and Control Pins
0.98V to 1.02V
0.0V to 3.45V
on B Port
0.0V to 3.45V
HIGH Level Output Current (IOH)
A Port
−24 mA
LOW Level Output Current (IOL)
A Port
+24 mA
B Port
+50 mA
Operating Temperature (TA)
−40°C to +85°C
Note 4: Absolute Maximum continuous ratings are those values beyond
which damage to the device may occur. Exposure to these conditions or
conditions beyond those indicated may adversely affect device reliability.
Functional operation under absolute maximum rated conditions in not
implied.
Note 5: IO Absolute Maximum Rating must be observed.
Note 6: Unused inputs must be held HIGH or LOW.
DC Electrical Characteristics
Over Recommended Operating Free-Air Temperature Range, VREF = 1.0V (unless otherwise noted).
Symbol
Test Conditions
Min
VIH
VIL
VREF
VIK
VOH
VOL
II
IOFF
II(hold)
IOZH
IOZL
B Port
Others
B Port
Others
GTLP (Note 8)
GTL
A Port
VCC = 3.15V
VCC, VCCQ = Min to Max (Note 9)
VCC = 3.15V
A Port
B Port
VCC, VCCQ = Min to Max (Note 9)
VCC = 3.15V
VCC = 3.15V
Control Pins
A Port
VCC = Min to Max (Note 9)
VCC = 3.45V
B Port
VCC = 3.45V
A Port and Control Pins VCC = 0
A Port
VCC = 3.15V
A Port
B Port
A Port
B Port
VCC = 3.45V
VCC = 3.45V
VREF +0.05
2.0
0.0
II = −18 mA
IOH = −100 µA
IOH = −8 mA
IOH = -24mA
IOL = 100 µA
IOL = 24mA
IOL = 40 mA
IOL = 50 mA
VI = 3.45V or 0V
VI = 0V
VI = 3.45
VI = VCC
VI = 0
VI or VO = 0 to 3.45V
VI = 0.8V
VI = 2.0V
VO = 3.45
VO = 1.5V
VO = 0V
VO = 0.55V
VCC –0.2
2.4
2.0
75
Typ
(Note 7)
1.0
0.8
Max
VTT
VREF − 0.05
0.8
−1.2
0.2
0.5
0.40
0.55
±5
−10
10
5
−5
30
−75
10
5
−10
−5
Units
V
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
µA
www.fairchildsemi.com
4
4페이지 Test Circuits and Timing Waveforms
Test Circuit for A Outputs
Test Circuit for B Outputs
Test
S
tPLH/tPHL Open
tPLZ/tPZL 6V
tPHZ/tPZH GND
Note A: CL includes probes and Jig capacitance.
Voltage Waveform - Propagation Delay Times
Note B: For B Port, CL = 30 pF is used for worst case.
Voltage Waveform - Setup and Hold Times
Voltage Waveform - Pulse Width
Voltage Waveform - Enable and Disable times
Output Waveform 1 is for an output with internal conditions such that the
output is LOW except when disabled by the control output.
Output Waveform 2 is for an output with internal conditions such that the
output is HIGH except when disabled by the control output.
Input and Measure Conditions
A or LVTTL B or GTLP
Pins
Pins
VinHIGH
3.0
1.5
VinLOW
0.0
0.0
VM 1.5 1.0
VX VOL + 0.3V N/A
VY VOH − 0.3V N/A
All input pulses have the following characteristics: Frequency = 10MHz, tRISE = tFALL = 2 ns (10% to 90%), ZO = 50Ω.
The outputs are measured one at a time with one transition per measurement.
7 www.fairchildsemi.com
7페이지 | |||
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부품번호 | 상세설명 및 기능 | 제조사 |
GTLP18T612 | 18-Bit LVTTL/GTLP Universal Bus Transceiver | Fairchild Semiconductor |
GTLP18T612MEA | 18-Bit LVTTL/GTLP Universal Bus Transceiver | Fairchild Semiconductor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |