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GTLP6C816 데이터시트 PDF




Fairchild Semiconductor에서 제조한 전자 부품 GTLP6C816은 전자 산업 및 응용 분야에서
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부품번호 GTLP6C816 기능
기능 GTLP-to-TTL 1:6 Clock Driver
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GTLP6C816 데이터시트, 핀배열, 회로
June 1998
Revised October 1998
GTLP6C816
GTLP-to-TTL 1:6 Clock Driver
General Description
The GTLP6C816 is a clock driver that provides TTL to
GTLP signal level translation (and vice versa). The device
provides a high speed interface between cards operating at
TTL logic levels and a backplane operating at GTLP logic
levels. High speed backplane operation is a direct result of
GTLP’s reduced output swing (<1V), reduced input thresh-
old levels and output edge rate control. The edge rate con-
trol minimizes bus settling time. GTLP is a Fairchild
Semiconductor derivative of the Gunning Transceiver logic
(GTL) JEDEC standard JESD8-3.
Fairchild’s GTLP has internal edge-rate control and is pro-
cess, voltage, and temperature (PVT) compensated. Its
function is similar to BTL and GTL but with different output
levels and receiver threshold. GTLP output LOW level is
typically less than 0.5V, the output level HIGH is 1.5V and
the receiver threshold is 1.0V.
Features
s Interface between TTL and GTLP logic levels
s Edge Rate Control to minimize noise on the GTLP port
s Power up/down high impedance for live insertion
s 1:6 fanout clock driver for TTL port
s 1:2 fanout clock driver for GTLP port
s TTL compatible driver and control inputs
s Flow through pinout optimizes PCB layout
s Open drain on GTLP to support wired-or connection
s Recommended Operating Temperature 40°C to +85°C
Ordering Code:
Order Number Package Number Package Description
GTLP6C816MTC MTC24
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pin Descriptions
Connection Diagram
Pin Names
Description
TTLIN, GTLPIN Clock Inputs (TTL and GTLP respectively)
OEB
Output Enable (Active LOW)
GTLP Port (TTL Levels)
OEA
Output Enable (Active LOW)
TTL Port (TTL Levels)
VCCT.GNDT
VCC
GNDG
TTL Output Supplies (5V)
Internal Circuitry VCC (5V)
OBn GTLP Output Grounds
VREF
OA0–OA5
Voltage Reference Input
TTL Buffered Clock Outputs
OB0–OB1
GTLP Buffered Clock Outputs
© 1998 Fairchild Semiconductor Corporation DS500129.prf
www.fairchildsemi.com




GTLP6C816 pdf, 반도체, 판매, 대치품
DC Electrical Characteristics
Over Recommended Operating Free-Air Temperature Range, VREF = 1.0V (unless otherwise noted).
Typ
Symbol
Test Conditions
Min
(Note 4)
Max
Units
VIH GTLPIN
Others
VREF +0.05
2.0
VTT V
VIL GTLPIN
Others
0.0
VREF 0.05
V
0.8
VREF
GTLP
(Note 5) GTL
1.0
V
0.8
VTT GTLP
(Note 5) GTL
1.5
V
1.2
VIK
VOH
OAn-Port
VOL OAn-Port
VOL OBn-Port
II TTLIN/
Control Pins
GTLPIN
IOFF
TTLIN
VCC = 4.75V
VCC = 4.75V
VCC = 4.75V
VCC = 4.75V
VCC = 5.25V
VCC = 5.25V
VCC = 0
II = −18 mA
IOH = −100 µA
IOH = −18 mA
IOH = −24 mA
IOL = 100 µA
IOL = 18 mA
IOL = 24 mA
IOL = 100 µA
IOL = 34 mA
VI = 5.25V
VI = 0V
VI = VTT
VI = 0
VI or VO = 0V to
5.25V
VCC0.2
2.4
2.2
1.2
0.2
0.4
0.5
0.2
0.65
5
5
5
5
100
V
V
V
V
µA
µA
µA
IOZH
IOZL
ICC
OAn-Port
OBn-Port
OAn-Port
OAn or
OBn Ports
VCC = 5.25V
VCC = 5.25V
VCC = 5.25V
VO = 5.25V
VO = 1.5V
VO = 0
Outputs HIGH
Outputs LOW
5
µA
5
5 µA
7 18
7 20 mA
ICC
CIN
TTLIN
Control Pins/GTLPIN/
TTLIN
VI = VCC or GND
VCC = 5.25V
Outputs Disabled
VI = VCC2.1
VI = VCC or 0
7 20
6
3.7
mA
pF
COUT
OAn-Port
OBn-Port
VI = VCC or 0 7 pF
VI = VCC or 0
7
Note 4: All typical values are at VCC = 5.0V and TA = 25°C.
Note 5: GTLP VREF and VTT are specified to 2% tolerance since signal integrity and noise margin can be significantly degraded if these supplies are noisy.
In addition, VTT and RTERM can be adjusted to accommodate backplane impedances other than 50, within the boundaries of not exceeding the DC Abso-
lute IOL ratings. Similarly VREF can be adjusted to compensate for changes in VTT.
www.fairchildsemi.com
4

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GTLP6C816 전자부품, 판매, 대치품
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC24
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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