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25Q80BSIG 데이터시트 PDF




GigaDevice에서 제조한 전자 부품 25Q80BSIG은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 25Q80BSIG 자료 제공

부품번호 25Q80BSIG 기능
기능 Dual and Quad Serial Flash
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25Q80BSIG 데이터시트, 핀배열, 회로
25Q80BSIG
FEATURES
8M-bit Serial Flash
-1024K-byte
-256 bytes per programmable page
Standard, Dual, Quad SPI
-Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD#
-Dual SPI: SCLK, CS#, IO0, IO1, WP#, HOLD#
-Quad SPI: SCLK, CS#, IO0, IO1, IO2, IO3
High Speed Clock Frequency
-120MHz for fast read with 30PF load
-Dual I/O Data transfer up to 180Mbits/s
-Quad I/O Data transfer up to 360Mbits/s
Program/Erase Speed
-Page Program time: 0.7ms typical
-Sector Erase time: 100ms typical
-Block Erase time: 0.3/0.4/0.8s typical
-Chip Erase time: 8s typical
Flexible Architecture
-Sector of 4K-byte
-Block of 32/64/128K-byte
Low Power Consumption
-20mA maximum active current
-5uA maximum power down current
Software/Hardware Write Protection
-Write protect all/portion of memory via software
-Enable/Disable protection with WP# Pin
-Top or Bottom, Sector or Block selection
Minimum 100,000 Program/Erase Cycles
Note: 1.Please contact Gigadevice for details
Advanced security Features(1)
-16-Bit Customer ID
-Security Architecture
Single Power Supply Voltage
-Full voltage range:2.7~3.6V
http://www.DataSheet4U.net/
GENERAL DESCRIPTION
The GD25Q80 (8M-bit) Serial flash supports the standard Serial Peripheral Interface (SPI), and supports the
Dual/Quad SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (WP#), and I/O3 (HOLD#). The Dual I/O
data is transferred with speed of 180Mbits/s and the Quad I/O & Quad output data is transferred with speed of
360Mbits/s.
CONNECTION DIAGRAM
CS# 1
8
SO
WP#
27
Top View
36
VSS
45
8LEAD SOP/DIP
VCC
HOLD#
SCLK
SI
1
datasheet pdf - http://www.DataSheet4U.net/




25Q80BSIG pdf, 반도체, 판매, 대치품
Uniform Sector
Dual and Quad Serial Flash
GD25Q80
DEVICE OPERATION
SPI Mode
Standard SPI
The GD25Q80 features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS#), Serial
Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is latched on the rising
edge of SCLK and data shifts out on the falling edge of SCLK.
Dual SPI
The GD25Q80 supports Dual SPI operation when using the “Dual Output Fast Read” and “Dual I/O Fast Read” (3BH
and BBH) commands. These commands allow data to be transferred to or from the device at two times the rate of the
standard SPI. When using the Dual SPI command the SI and SO pins become bidirectional I/O pins: IO0 and IO1.
Quad SPI
The GD25Q80 supports Quad SPI operation when using the “Quad Output Fast Read”,” Quad I/O Fast Read”, “Quad
I/O Word Fast Read” (6BH, EBH, E7H) commands. These commands allow data to be transferred to or from the device at
four times the rate of the standard SPI. When using the Quad SPI command the SI and SO pins become bidirectional I/O
pins: IO0 and IO1, and WP# and HOLD# pins become IO2 and IO3. Quad SPI commands require the non-volatile Quad
Enable bit (QE) in Status Register to be set.
Hold
The HOLD# signal goes low to stop any serial communications with the device, but doesn’t stop the operation of write
status register, programming, or erasing in progress.
http://www.DataSheet4U.net/
The operation of HOLD, need CS# keep low, and starts on falling edge of the HOLD# signal, with SCLK signal being
low (if SCLK is not being low, HOLD operation will not start until SCLK being low). The HOLD condition ends on rising edge
of HOLD# signal with SCLK being low (If SCLK is not being low, HOLD operation will not end until SCLK being low).
The SO is high impedance, both SI and SCLK don’t care during the HOLD operation, if CS# drives high during HOLD
operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high and
then CS# must be at low.
Figure1. Hold Condition
CS#
SCLK
HOLD#
HOLD
HOLD
4
datasheet pdf - http://www.DataSheet4U.net/

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25Q80BSIG 전자부품, 판매, 대치품
Uniform Sector
Dual and Quad Serial Flash
GD25Q80
COMMANDS DESCRIPTION
All commands, addresses and data are shifted in and out of the device, beginning with the most significant bit on the
first rising edge of SCLK after CS# is driven low. Then, the one-byte command code must be shifted in to the device, most
significant bit first on SI, each bit being latched on the rising edges of SCLK.
See Table2, every command sequence starts with a one-byte command code. Depending on the command, this
might be followed by address bytes, or by data bytes, or by both or none. CS# must be driven high after the last bit of the
command sequence has been shifted in. For the command of Read, Fast Read, Read Status Register or Release from
Deep Power-Down, and Read Device ID, the shifted-in command sequence is followed by a data-out sequence. CS# can
be driven high after any bit of the data-out sequence is being shifted out.
For the command of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write Enable,
Write Disable or Deep Power-Down command, CS# must be driven high exactly at a byte boundary, otherwise the
command is rejected, and is not executed. That is CS# must driven high when the number of clock pulses after CS# being
driven low is an exact multiple of eight. For Page Program, if at any time the input byte is not a full byte, nothing will happen
and WEL will not be reset.
Command Name
Write Enable
Write Disable
Read Status Register
Read Status Register-1
Write Status Register
Read Data
Fast Read
Dual Output
Fast Read
Dual I/O
Fast Read
Quad Output
Fast Read
Quad I/O
Fast Read
Quad I/O Word
Fast Read(7)
Continuous Read Reset
Page Program
Sector Erase
Block Erase(32K)
Block Erase(64K)
Block Erase(128K)
Chip Erase
Program/Erase
Suspend
Program/Erase Resume
Deep Power-Down
Release From Deep
Power-Down, And
Read Device ID
Release From Deep
Power-Down
Byte 1
06H
04H
05H
35H
01H
03H
0BH
3BH
BBH
6BH
EBH
E7H
FFH
02 H
20H
52H
D8H
D2H
C7/60 H
75H
7AH
B9H
ABH
ABH
Byte 2
Table2. Commands
Byte 3
Byte 4
(S7-S0)
(S15-S8)
(S7-S0)
A23-A16
A23-A16
A23-A16
(S15-S8)
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
http://www.DataSheet4U.net/
A7-A0
A23-A8(2)
A23-A16
A7-A0
M7-M0(2)
A15-A8
(D7-D0)(1)
A7-A0
A23-A0
M7-M0(4)
A23-A0
M7-M0(4)
dummy(5)
dummy(6)
(D7-D0)(3)
(D7-D0)(3)
A23-A16
A23-A16
A23-A16
A23-A16
A23-A16
A15-A8
A15-A8
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
A7-A0
A7-A0
dummy
dummy
dummy
Byte 5 Byte 6
n-Bytes
(continuous)
(continuous)
(D7-D0)
dummy
dummy
(Next byte)
(D7-D0)
(D7-D0)(1)
(continuous)
(continuous)
(continuous)
dummy
(D7-D0)(3)
(continuous)
(continuous)
(continuous)
(continuous)
D7-D0
Next byte
(ID7-ID0)
(continuous)
7
datasheet pdf - http://www.DataSheet4U.net/

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부품번호상세설명 및 기능제조사
25Q80BSIG

Dual and Quad Serial Flash

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