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PDF S3056 Data sheet ( Hoja de datos )
| Número de pieza | S3056 | |
| Descripción | MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT | |
| Fabricantes | AMCC | |
| Logotipo |  |
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DEVICE
SMPEUCLITFIIC-RATAIOTEN SONET/SDH CLOCK RECOVERY UNIT
BMiUCLMTOI-SRAPTEECLSOCNLEOTC/KSDGHECNLEORCAKTORRECOVERY UNIT
®
S3056
S3056
FEATURES
• SiGe BiCMOS technology
• Complies with Bellcore and ITU-T specifica-
tions for jitter tolerance, jitter transfer and
jitter generation
• On-chip high frequency PLL with internal
loop filter for clock recovery
• Supports clock recovery for:
OC-48 (2488.32 Mbps),
Fibre Channel (2125 Mbps),
OC-24 (1244.16 Mbps),
Gigabit Ethernet (1250 Mbps),
Fibre Channel (1062.5 Mbps),
OC-12 (622.08 Mbps),
OC-3 (155.52 Mbps) NRZ data
• Selectable reference frequencies
19.44 MHz or 155.52 MHz
(or equivalent Fibre Channel/
Gigabit Ethernet frequencies)
• Lock detect—monitors frequency of
incoming data
• Low-jitter serial interface
• +3.3 V supply
• Compact 48 pin TQFP TEP package
• Typical power 620 mW
GENERAL DESCRIPTION
The function of the S3056 clock recovery unit is to
derive high speed timing signals for SONET/SDH-
based equipment. The S3056 is implemented using
AMCC’s proven Phase Locked Loop (PLL) technology.
Figure 1 shows a typical network application.
The S3056 receives an OC-48, OC-24, OC-12, OC-3,
Fibre Channel or Gigabit Ethernet scrambled NRZ sig-
nal and recovers the clock from the data. The chip
outputs a differential bit clock and retimed data.
The S3056 utilizes an on-chip PLL which consists
of a phase detector, a loop filter, and a Voltage
Controlled Oscillator (VCO). The phase detector
compares the phase relationship between the VCO
output and the serial data input. A loop filter con-
verts the phase detector output into a smooth DC
voltage, and the DC voltage is input to the VCO
whose frequency is varied by this voltage. A block
diagram is shown in Figure 2.
Figure 1. System Block Diagram
16 16
OTX
ORX S3056
S3057
16
S3056 ORX
OTX
S3057
16
October 31, 2000 / Revision J
1
1 page  
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
S3056
FIBRE CHANNEL
JITTER CHARACTERISTICS
Performance
The S3056 PLL complies with the jitter specifications
proposed for Fibre Channel equipment defined by the
fibre channel methodology for Jitter specification.
Input Jitter Tolerance
Input jitter tolerance is defined as the peak to
peak amplitude of sinusoidal jitter applied on the
input signal that causes an equivalent 1 dB opti-
cal/electrical power penalty. Fibre Channel input
jitter tolerance requirements are shown in
Table 3.
Jitter Generation
The jitter of the serial clock and serial data outputs
shall not exceed the value specified in Table 4 when
a serial data input with no jitter is presented to the
serial data inputs.
Table 3. Input Jitter Tolerance Specification at node αR
Parameters
Description
tFDJ Frequency Dependent Jitter Tolerance (637 kHz to ≥ 5 MHz)
tDJ Deterministic Jitter Tolerance (637 kHz – 531 MHz)
tRJ Random Jitter (637 kHz – 531 MHz)
tTJ Total Jitter
Min
0.10
0.38
0.22
0.70
Max Units
– UI p-p
– UI p-p
– UI p-p
– UI p-p
Table 4. Total Jitter Generation Specification at node αT
Parameters
Description
DJ Deterministic Jitter
TJ Total Jitter
Min Max Units
0.08 UI p-p
0.23 UI p-p
Figure 5. Fibre Channel System Node Definition
SYSTEM
HOST ADAPTOR
SERDES
αT = Component Transmitter Node
Componet Receiver Node = αR
SYSTEM
STORAGE
DISK DRIVE
SERDES
October 31, 2000 / Revision J
BACKPLANE
PBC
REPEAETERS
CABLES
CONNECTORS
5
5 Page 
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
Table 7. Performance Specifications (Continued)
Parameter
Min Typ
tSU
OC-48/Fibre Channel (2125 Mbps)
OC-24/Fibre Channel (1062.5 Mbps)
OC-12
OC-3
tH
100
250
500
2500
OC-48/Fibre Channel (2125 Mbps)
OC-24/Fibre Channel (1062.5 Mbps)
OC-12
OC-3
100
250
500
2500
Max
Units
ps
ps
Condition
See Figure 8.
See Figure 8.
S3056
Figure 8. Receiver Output Timing Diagram
SERCLKOP
SERDATOP/N
50%
tSU tH
Note: Output propagation delay time of high speed CML outputs is the time in pico seconds from the cross-over point of the
reference signal to the cross-over point of the output.
Table 8. Jitter Tolerance Specifications
Parameter
Min Typ Max Units Conditions
Jitter Tolerance
STS-48
0.4 0.5
UI
1 MHz < f < 5 MHz
Data Pattern = 27-1 PRBS
Jitter Tolerance
STS-24
Jitter Tolerance
STS-12
0.4 0.6
UI
250 kHz < f < 5 MHz
Data Pattern = 27-1 PRBS
Jitter Tolerance
STS-3
0.4 0.8
UI
65 kHz < f < 1 MHz
Data Pattern = 27-1 PRBS
October 31, 2000 / Revision J
11
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet S3056.PDF ] | |
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