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ELIS-1024 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 ELIS-1024
기능 Enhanced High Performance Linear CMOS Image Sensor
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ELIS-1024 데이터시트, 핀배열, 회로
Silicon Video Inc.
P.O. Box 4902, Ithaca, NY 14852-4902, .TEL: 607.756.5200, FAX: 607.756.5319
www.siliconvideo.biz , sales@siliconvideo.biz
ELIS-1024
Enhanced High Performance Linear CMOS Image Sensor
The ELIS-1024 image sensor is a high performance, very low noise linear image sensor designed for a
wide variety of applications including:
P/N: ELIS-1024A-LG
16-pin LCC package
Spectroscopy
Bar Code Reading
Edge Detection
Contact Scanning
Optical Character Recognition
Encoding
Position Detection
And more.......
Description
The ELIS-1024 Linear Image Sensor consists of an array of high performance, low dark current photo-
diode pixels. The sensor features sample and hold capability, selectable resolution and advanced power
management. The device can operate at voltages as low as 2.8V making it ideal for portable
applications. A key feature over traditional CCD technology is that the device can be read and reread
Non-Destructively, allowing the user to maximize signal to noise and dynamic range. Internal logic
automatically reduces power consumption when lower resolution settings are selected. A low power
standby mode is also available to reduce system power consumption when the imager is not in use.
Key Features
Low Cost
Single Voltage Operation, Wide Operating Range
Selectable Resolutions of 1024, 512, 256 and 128 pixels
Very Low Power via Intelligent Power Management and Low-Power Standby Mode
Sample and Hold
Full Frame Shutter and Dynamic Pixel Reset (DPR) Modes
High Sensitivity
High Signal to Noise, very low dark current
Non-Destructive Read mode, extremely low noise capable via signal averaging
Completely Integrated Timing and Control
PDS0004 Rev. A
© Silicon Video, Inc. 2003
Subject to change without notice.
Page 1 of 10




ELIS-1024 pdf, 반도체, 판매, 대치품
Absolute maximum ratings, TA = 25°C unless otherwise noted, see Note 1, below. †
Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 6.0 V
Digital input current range, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –16 mA to 16 mA
Operating case temperature range, TC (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 50°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 20°C to 85°C
Humidity range, RH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0-100%, non-condensing
Lead temperature 1.5 mm (0.06 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235°C
Exceeding the ranges specified under “absolute maximum ratings” can damage the device. The values given are for stress ratings
only. Operation of the device at conditions other than those indicated under “recommended operating conditions” is not implied.
Exposing the device to absolute maximum rated conditions for extended periods may affect device reliability and performance.
NOTES: 1. Voltage values are with respect to the device GND terminal.
2. Case temperature is defined as the surface temperature of the package measured directly over the integrated circuit.
1.2000
1.0000
0.8000
0.6000
0.4000
0.2000
0.0000
QE RESPONSE
Wavelength
Note: Data below 350nm not measured, but device is sensitive to 200 nm. The QE peaks at 675nm. Shown for un-filtered
and un-covered device.
PDS0004 Rev. A
© Silicon Video, Inc. 2003
Subject to change without notice.
Page 4 of 10

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ELIS-1024 전자부품, 판매, 대치품
Figure 2: Detailed DATA Pulse Timing Diagram.
Non-Destructive Readout (NDRO)
NDRO mode is similar to the standard mode of operation except that the pixels are readout
multiple times for a single integration time. The required signal timings are shown in Figure 3.
CLK
RST
SHT
DATA
VIDEO
tRST
t int1
Video_Out1
X Clock Cycles
Figure 3: Non-Destructive Readout Timing Diagram.
Video_Out1
X Clock Cycles
Dynamic Pixel Reset (DPR) Mode Timing (RM = 1)
In DPR mode the pixels are reset by internal signals, which eliminates the need for using the external
reset pin. When operating in DPR mode RST must be held low otherwise the internal logic will be
held in reset. However, RST does NOT reset the pixels in DPR mode. Since the pixels are
continuously integrating (except the one clock cycle they are being reset) the SHT pin should always
be held high. The first frame readout will be invalid because the pixels will have been integrating
for an unknown period of time. Valid video will be generated during the second frame. The
required signal timings are illustrated in Figure 4.
CLK
RST
SHT
DATA
VIDEO
Pixel1_Readout
Pixel1_Reset
Pixel1_Readout
Pixel1_Reset
tCLK
tDATA
Pixel1_t int
Frame1
Frame2
X Clock Cycles
X Clock Cycles
Figure 4: DPR Mode Timing Diagram.
Pixel 1 was used as an example to show the key timing situations. During the first clock cycle after
DATA is high pixel 1 is readout. Then while pixel 2 is being readout during the second clock cycle
PDS0004 Rev. A
© Silicon Video, Inc. 2003
Subject to change without notice.
Page 7 of 10

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