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GM71C17400CLT-5 데이터시트 PDF




Hynix Semiconductor에서 제조한 전자 부품 GM71C17400CLT-5은 전자 산업 및 응용 분야에서
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부품번호 GM71C17400CLT-5 기능
기능 CMOS DYNAMIC RAM
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GM71C17400CLT-5 데이터시트, 핀배열, 회로
GM71C(S)17400C/CL
4,194,304 WORDS x 4 BIT
CMOS DYNAMIC RAM
Description
The GM71C(S)17400C/CL is the new
generation dynamic RAM organized 4,194,304
words x 4 bit. GM71C(S)17400C/CL has
realized higher density, higher performance and
various functions by utilizing advanced CMOS
process technology. The GM71C(S)17400C/CL
offers Fast Page Mode as a high speed access
mode. Multiplexed address inputs permit the
GM71C(S)17400C/CL to be packaged in a
standard 300 mil 24(26) pin SOJ, and a standard
300 mil 24(26) pin plastic TSOP II. The
package size provides high system bit densities
and is compatible with widely available
automated testing and insertion equipment.
System oriented features include single power
supply 5.0V+/-10% tolerance, direct interfacing
capability with high performance logic families
such as Schottky TTL.
Pin Configuration
24(26) SOJ
Features
* 4,194,304 Words x 4 Bit Organization
* Fast Page Mode Capability
* Single Power Supply (5.0V+/-10%)
* Fast Access Time & Cycle Time
(Unit: ns)
GM71C(S)17400C/CL-5
GM71C(S)17400C/CL-6
GM71C(S)17400C/CL-7
tRAC tCAC tRC
50 13 90
60 15 110
70 18 130
tPC
35
40
45
* Low Power
Active : 660/605/550mW (MAX)
Standby : 11mW (CMOS level : MAX)
: 0.83mW (L-version : MAX)
* RAS Only Refresh, CAS before RAS Refresh,
Hidden Refresh Capability
* All inputs and outputs TTL Compatible
* 2048 Refresh Cycles/32ms
* 2048 Refresh Cycles/128ms (L-version)
* Battery backup operation (L-version)
* Test function : 16bit parallel test mode
24(26) TSOP II
VCC 1
I/O1 2
I/O2 3
WE 4
RAS 5
NC 6
A10 8
A0 9
A1 10
A2 11
A3 12
VCC 13
26 VSS
25 I/O4
24 I/O3
23 CAS
22 OE
21 A9
19 A8
18 A7
17 A6
16 A5
15 A4
14 VSS
VCC 1
I/O1 2
I/O2 3
WE 4
RAS 5
A11 6
A10 8
A0 9
A1 10
A2 11
A3 12
VCC 13
26 VSS
25 I/O4
24 I/O3
23 CAS
22 OE
21 A9
19 A8
18 A7
17 A6
16 A5
15 A4
14 VSS
(Top View)
Rev 0.1 / Apr’01




GM71C17400CLT-5 pdf, 반도체, 판매, 대치품
GM71C(S)17400C/CL
Capacitance (VCC = 5.0V+/-10%, TA = 25C)
Symbol
Parameter
Min Max Unit
CI1 Input Capacitance (Address)
- 5 pF
CI2 Input Capacitance (Clocks)
- 7 pF
CI/O Output Capacitance (Data-In/Out)
- 7 pF
Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. CAS = VIH to disable DOUT.
Note
1
1
1, 2
AC Characteristics (VCC = 5.0V+/-10%, Vss=0V, TA = 0 ~ 70C, Notes 1, 2, 18,19)
Test Conditions
Input rise and fall times : 5ns
Input timing reference levels : 0.8V, 2.4V
Output timing reference levels : 0.4V, 2.4V
Output load : 2 TTL gate + CL (100pF)
(Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters)
Symbol
Parameter
GM71C(S)17400 GM71C(S)17400 GM71C(S)17400
C/CL-5
C/CL-6
C/CL-7
Min Max Min Max Min Max
Unit
Note
tRC Random Read or Write Cycle Time
tRP RAS Precharge Time
90 - 110 - 130 -
30 - 40 - 50 -
ns
ns
tCP CAS Precharge Time
7 - 10 - 10 - ns
tRAS RAS Pulse Width
tCAS CAS Pulse Width
tASR Row Address Set up Time
tRAH Row Address Hold Time
tASC Column Address Set-up Time
tCAH Column Address Hold Time
tRCD RAS to CAS Delay Time
tRAD RAS to Column Address Delay Time
tRSH RAS Hold Time
tCSH CAS Hold Time
tCRP CAS to RAS Precharge Time
tODD
OE to DIN Delay Time
tDZO OE Delay Time from DIN
tDZC CAS Delay Time from DIN
tT Transition Time (Rise and Fall)
50 10,000 60 10,000 70 10,000 ns
13 10,000 15 10,000 18 10,000 ns
0 - 0 - 0 - ns
7 - 10 - 10 - ns
0 -0
7 - 10
17 45 20
12 30 15
-0
- 15
45 20
30 15
-
-
52
35
ns
ns
ns
ns
13 - 15
50 - 60
- 18
- 70
-
-
ns
ns
5 - 5 - 5 - ns
13 - 15 - 18 - ns
0 -0
0 -0
3 50 3
-0
-0
50 3
-
-
50
ns
ns
ns
3
4
5
6
6
7
Rev 0.1 / Apr’01

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GM71C17400CLT-5 전자부품, 판매, 대치품
GM71C(S)17400C/CL
Fast Page Mode Read-Modify-Write Cycle
Symbol
Parameter
GM71C(S)17400 GM71C(S)17400 GM71C(S)17400
C/CL-5
C/CL-6
C/CL-7
Min Max Min Max Min Max
Unit
tPRWC
tCPW
Fast Page Mode Read-Modify-Write
Cycle Time
WE Delay Time from CAS Precharge
76 - 85 - 96 - ns
53 - 60 - 68 - ns
Note
14
Test Mode Cycle 19
Symbol
Parameter
tWTS Test Mode WE Setup Time
tWTH Test Mode WE Hold Time
GM71C(S)17400 GM71C(S)17400 GM71C(S)17400
C/CL-5
C/CL-6
C/CL-7
Min Max Min Max Min Max
Unit
0- 0- 0-
ns
10 - 10 - 10 -
ns
Note
Refresh
Symbol
Parameter
tREF Refresh Period
tREF Refresh Period (L - version)
GM71C(S)17400 GM71C(S)17400 GM71C(S)17400
C/CL-5
C/CL-6
C/CL-7
Min Max Min Max Min Max
Unit
- 32 - 32 - 32 ms
- 128 - 128 - 128 ms
Note
2048
cycles
2048
cycles
Rev 0.1 / Apr’01

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