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L6180 데이터시트 PDF




STMicroelectronics에서 제조한 전자 부품 L6180은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


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부품번호 L6180 기능
기능 OCTAL LINE RECEIVER
제조업체 STMicroelectronics
로고 STMicroelectronics 로고


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L6180 데이터시트, 핀배열, 회로
L6180
L6181
OCTAL LINE RECEIVER FOR:
- EIA STD RS232D
RS423A
- CCIT
RS422A
V.10
V.11
V.28
X.26
NO EXTERNAL COMPONENTS
INPUT FAIL SAFING CAPABILITY
HIGH CROSSTALK REJECTION
L6180 DATA RATE < 100KBIT/S
L6181 DATA RATE < 1MBIT/S
50V EOS OUTPUT PROTECTION
OCTAL LINE RECEIVER
ADVANCE DATA
DIP 28
PLCC 28
ORDERING NUMBER: L6180A DIP 28
L6180D PLCC28
L6181A DIP 28
L6181D PLCC28
DESCRIPTION
L6180/1 is an octal line receiver in a plastic DIP
or PLCC designed to meet a wide range of digital
communications requirements as outlined in the
EIA standards RS232A without additional compo-
nents, as well as the low speed applications of
RS422A.
BLOCK DIAGRAM
The receiver meets the CCIT recommendations
V.10, V.11, X.26 and V.28 low speed applications
(below 100KBS).
A low pass filter on the input starts to roll off at a
frequency of 100KHz.
October 1993
1/10
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.




L6180 pdf, 반도체, 판매, 대치품
L6180 - L6181
ELECTRICAL CHARACTERISTICS (VCC = 5V ±5%; VCM = -7 to 7V; Tamb = 0 to 70°C;
VSS = -9 to 13.5V; VDD = 9 to 13.5V; unless otherwise specified.)
Symbol
fR
Parameter
Frequency Rejected
(No Receiver Output)
Test Condition
VIN = 2Vpp;
(see fig. 8 and note 7)
Min.
Typ.
5
Max.
Unit
MHz
Note:
1) The algebric convention, where the less positive (more negative) is designed the minimum
2) With the voltage VIA or (VIB) ranging between ±15V, while VIB or (VIA) is open or grounded, the resultant input current IIA or (IIB) shall remain
within the shaded region shown in the graph in Fig.1.
3) Either Point B’ or Point A’ is grounded in Figure 1
4) VICC measured from grounded to (+) input with (-) input grounded
VICC measured from grounded to (+) input with (-) input grounded
5) Not more than one output should be shorted at a time and for less than 1 seond
6) The sum of the product of the maximum supply currents and voltages cannot exceed themaximum power dissipation
7) A: The conditions for the inpit switching from VIOCL to VIOCH mode is: Vid in start bit ”spacing condition”for less than TpVioch (5ms).
B: The conditions for the input switching from VIOCH to VIOCL mode is: Vid > WW2 for greater than TpVIOCL (200ms)
8) An example of a frequency response plot meeting the rejection/acceptance requirements is provided in figure 8.
LINE TRANSIENT IMMUNITY (Considering the following cases; powered ON, Powered OFF-LOW im-
pedance power supply and powered OFF-HIGH impedance supply)
Symbol
ESD
Static
Parameter
EOS
Stress
Test Condition
tested per MIL-STD-883
(see note 9)
transient pulse both polarities
for 100µs (see note 9 and Fig. 2)
Min.
2
50
Typ.
Max.
Note:
9) All pins are required to withstand this parameters.
10) Input pins are required to withstand fig.2 without any degradation to the circuit.
11) The balance test requirement can be met by use of a current limit circuit which reduces the input bias current Iib (see figure 7)
for input voltages below a threshold voltage given by (Iib x 1K) - 400mV.
Unit
KV
V
Figure 1: Input Current Voltage Mesurements
4/10

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L6180 전자부품, 판매, 대치품
Figure 7: Receiver input Balance Measurement
L6180 - L6181
INPUT BALANCE MEASUREMENT
The balance of the receiver input voltage-current
characteristics and bias voltages shall be such
that the receiver will remain in the intended binary
state when a differential voltage Vi of 400mV is
applied through 500±1% to each input terminal,
as shown above, and Vcm is varied between -7
and +7V.
When the polarity of Vi is reversed, the opposite
binary state shall be maintained under the same
conditions. Maintain input balance with input B
common with another receiver.
The voltage input (VIN) rejection is checked at the
center point between the High Operating Thresh-
old (Vth2) and the Low OperatingThreshold (Vth1)
Figure 8: High Frequency Signal Rejection
7/10

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