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PDF L6223 Data sheet ( Hoja de datos )
| Número de pieza | L6223 | |
| Descripción | DMOS PROGRAMMABLE HIGH SPEED UNIPOLAR STEPPER MOTOR DRIVER | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de L6223 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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L6223
DMOS PROGRAMMABLE
HIGH SPEED UNIPOLAR STEPPER MOTOR DRIVER
HIGH EFFICIENCY UNIPOLAR STEPPER
MOTOR DRIVER
HIGH SPEED UNIPOLAR STEPPER MOTOR
DRIVER
SUPPLY VOLTAGE UP TO 46V
PHASE CURRENT UP TO 1A
UP TO 2A/PHASE IN DUAL CONFIGURA-
TION
PARALLEL CMOS µP INTERFACE FOR
FULL/HALF STEP MOTOR ROTATION
SERIAL INTERFACE FOR 6 BIT PROGRAM-
MING
CLOSE/OPEN LOOP, 8 PWM CURRENT
LEVELS
DUAL PWM FREQUENCY SELECTION
INPUT BIDIRECTIONALLY PROTECTED
THERMAL SHUTDOWN
DESCRIPTION
The L6223 is a programmable integrated system
for driving a unipolar stepper motor. It is realized
in Multipower BCD technology. The DMOS output
BLOCK DIAGRAM
MULTIPOWER BCD TECHNOLOGY
POWERDIP
16+2+2
ORDERING NUMBER : L6223
stage, realized by a single upper DMOS switch
and four lower DMOS, can deliver up to 1A/phase
with motor supply voltages up to 46V.
All inputs are CMOS and microprocessor compat-
ible. An internal 6-bit shift register allows the de-
vice to be programmed to select different duty cy-
cles in open loop mode and different chopping
frequencies in closed loop mode. When the cur-
rent control is in closed loop mode it is also possi-
ble to select a reduced current chopping level to
optimize system efficiency. The L6223 is de-
March 1998
1/33
1 page  
L6223
ELECTRICAL CHARACTERISTICS (Continued)
Symbol
Parameter
Test conditions
Min Typ Max Unit
SWITCHING TIMING
t2, t4
Fall/Rise Time (IN1, 2, 3, 4)
t1, t3
tdPWM
Input-Output Delay
(IN1, 2, 3, 4)
Close Loop PWM
Control Delay
R(load) = 39 Ω (Fig. 5)
Pure Resistive Load to VS
R(load) = 39 Ω (Fig. 5)
Pure Resistive Load to VS
(Fig. 4) Note 1
250 ns
700 ns
1 µs
PROGRAMMING TIMING
t1 Loading Time
(Fig. 6)
1.7
t2 Protection Time
(Fig. 6) Note 2
0.2
t3 Data Set-up
(Fig. 6)
0
t4 Data Hold
(Fig. 6)
1.6
t5 Setting Time
(Fig. 6)
200
Note 1) Upper DMOS turn ON delay when the signal is applied at the input comparator (point A in Fig. 4).
Note 2) Internal clock pulse is generated only if IN1...IN4 stay Low for almost 0.2 µs. This delay avoids undesirable programmings.
µs
µs
ns
µs
ns
Figure 1: Output leakage IOL Test Circuit
Figure 2a: Source Output DMOS RDS(ON) Test
Circuit
5/33
5 Page 
Table 6
C2 C3 t(ON)/t(OSC)*
L L 75
L H 50
H L 100
H H Output Disabled
*) RC discharge time percentage
Table 7
C4
L
H
L6223
Chopping Frequency
20kHz
10kHz
L6223 Operating Configuration vs. 6bits Shift Register Programming (External RC network: R =
18kΩ C = 3,3nF)
Full/Simpl. Close Loop
Close Loop
SHIFT REGISTER bITS
Operation
Frequency Open Loop
Current
Nr C5 C4 C3 C2 C1 C0
Mode
(kHz)
t(ON) [%]
Level [%]
00 0 0 0 0 0
S
20 75 40%
10 0 0 0 0 1
20 0 0 0 1 0
30 0 0 0 1 1
40 0 0 1 0 0
S
S
S
S
20 75 70%
20 75 55%
20 75 85%
20 100 40%
50 0 0 1 0 1
60 0 0 1 1 0
70 0 0 1 1 1
80 0 1 0 0 0
S
S
S
S
20 100 70%
20 100 55%
20 100 85%
20 50 40%
90 0 1 0 0 1
10 0 0 1 0 1 0
11 0 0 1 0 1 1
12 0 0 1 1 0 0
13 0 0 1 1 0 1
S
S
S
S
S
20 50 70%
20 50 55%
20 50 85%
20
DISABLED
40%
20
DISABLED
70%
14 0 0 1 1 1 0
15 0 0 1 1 1 1
16 0 1 0 0 0 0
17 0 1 0 0 0 1
18 0 1 0 0 1 0
19 0 1 0 0 1 1
20 0 1 0 1 0 0
21 0 1 0 1 0 1
22 0 1 0 1 1 0
23 0 1 0 1 1 1
24 0 1 1 0 0 0
25 0 1 1 0 0 1
26 0 1 1 0 1 0
27 0 1 1 0 1 1
28 0 1 1 1 0 0
29 0 1 1 1 0 1
30 0 1 1 1 1 0
31 0 1 1 1 1 1
32 1 0 0 0 0 0
33 1 0 0 0 0 1
34 1 0 0 0 1 0
35 1 0 0 0 1 1
36 1 0 0 1 0 0
37 1 0 0 1 0 1
38 1 0 0 1 1 0
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
F
F
F
F
F
F
F
20
DISABLED
55%
20
DISABLED
85%
10 75 40%
10 75 70%
10 75 55%
10 75 85%
10 100 40%
10 100 70%
10 100 55%
10 100 85%
10 50 40%
10 50 70%
10 50 55%
10 50 85%
10
DISABLED
40%
10
DISABLED
70%
10
DISABLED
55%
10
DISABLED
85%
20 75 40%
20 75 70%
20 75 55%
20 75 85%
20 100 40%
20 100 70%
20 100 55%
11/33
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet L6223.PDF ] | |
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