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PDF L6280 Data sheet ( Hoja de datos )
| Número de pieza | L6280 | |
| Descripción | THREE CHANNELS MULTIPOWER DRIVER SYSTEM | |
| Fabricantes | STMicroelectronics | |
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L6280
THREE CHANNELS MULTIPOWER DRIVER SYSTEM
PROGRAMMABLE
(CHANNELS 1 AND 2)
CONFIGURATION
OUTPUT CURRENT UP TO 1A (CHANNELS
1 AND 2)
1 SENSE PER CHANNEL
OUTPUT CURRENT CHANNEL 3 UP TO 3A
DIRECT INTERFACE TO MICROPROCESSOR
C-MOS COMPATIBLE INPUT
INTERNAL DC-DC CONVERTER FOR LOGIC
SUPPLY (+5V)
POWER FAIL
WATCHDOG MANAGEMENT
THERMAL PROTECTION
VERY LOW DISSIPATED POWER (SUIT-
ABLE FOR USE IN BATTERY SUPPLIED AP-
PLICATIONS)
DESCRIPTION
The L6280 is a multipower driver system for motor
and solenoid control applicatios that connects di-
rectly to a microprocessor bus. Realized in Mul-
tipower BCD technology -- which combines isolated
DMOS transistors, CMOS & bipolar circuits on the
ADVANCE DATA
MULTIPOWER BCD TECHNOLOGY
PLCC44
ORDERING NUMBER: L6280
same chip -- it integrates two 1A motor drivers
(channels 1 & 2) a 3A solenoid driver (channel 3)
and a 5V switchmode power supply.
All of the drivers in the L6280 are controlled by a
microprocessor which loads commands and
reads diagnostic information, treating the device
as a peripheral. Channels 1 and 2 feature a pro-
grammable output DMOS transistor configuration
that can be set during the initialization phase.
Thanks to very low dissipation of its DMOS power
stages the L6280 needs no heatsink and is pack-
aged in a 44-lead PLCC package.
BLOCK DIAGRAM
January 1992
1/26
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1 page  
L6280
ELECTRICAL CHARACTERISTICS (continued)
Symbol
VFLSD
tCW
tWPW
tSU
tDH
tWC
Parameter
Internal Clamp Diode Forward
Volt. CH3
Chip Seletion to End of Write
Write Pulse Width
Data Set-up Time
Data Hold-up Time
Write Cycle Time
Test Condition
@ IDS = 1A (Fig. 5)
(Fig. 6)
(Fig. 6)
(Fig. 6)
(Fig. 6)
(Fig. 6)
Min.
Typ.
Max.
1.1
Unit
V
700 ns
700 ns
700 ns
0 ns
2.7 ms
Notes:
1) When driving a unipolar stepper motor the Power Supply Voltage must be lower than 24V.
2) A lower Supply Voltage than the Power Fail threshold disables the Step Down Power Supply (see Fig.2)
3) The minimum output current equals the half of the peak-to-peak current ripple
4) tWD ≅ CWD x 1.5 /50 x 10 -6 (sec)
5) tD ≅ CD x 3.5 /50 x 10 -6 (sec)
6) tC≅ COSC x Rint. (sec); Rint. = 600Ω ± 30%
Figure 1: Drain Lekage Current Equivalent Test
Circuit . The Gate-to-Source Voltage
VGS is below the Switch-Off
Threshold.
Figure 3: Typical Normalized RDS(ON) vs.
Junction Temperature
5/26
5 Page 
Digital/Analog Converters (DACs)
The output current levels are programmed by
5DACs each with 3 bit resolution. Channels 1 and
2 each have 2 DACs, one for the left part of the
output stage and the other for the right part.
When the output stage is used to drive only one
load (as with DC motors), the L6280 uses only
the right register. Channel 3 has only 1 DAC.
Microstepping operation is easily performed with
channels 1 and 2. The value of each DAC can be
changed in two ways:
a) the new value can be directly generated by
the microprocessor and then loaded into the
specified DAC;
b) the value of a DAC can be incremented or
decremented by 1; in this case the microproc-
essor during acceleration or deceleration has
only to indicate the DAC on which operate
and the type of the operation, reducing the
CPU’s burden.
The correspondence between the DAC value and
the Vref level is shown in table 1.
Table 1
D2 D1 D0 Vref UNIT
1 1 11
V
1
1
0 0.875
V
1 0 1 0.75 V
1
0
0 0.625
V
0 1 1 0.5
V
0
1
0 0.375
V
0 0 1 0.25 V
0
0
0 0.125
V
Iload = 0 is obtained by disabling all low-side driv-
ers.
Turn ON/OFF Characteristics and Program Se-
quence
During power-on the Switchmode Power Supply
output stage is turned OFF till VS reaches VPFth.
The pin Reset Out is held low and remains low till
VSS is < VSSFth (the power stages and the logic of
the L6280 are disabled.
Not correct signals coming from the microproces-
sor are then ignored; the microprocessor on the
other hand, receives a low state signal from the
Reset Out pin. When the VSS output is stabilized
during a delay tD set by the CD capacitor, the pin
Reset Out goes to the high level; the microproc-
essor is enabled to work while the L6280 is in
stand-by waiting for a keyword and initialization
sequence. Every command that arrives before the
keyword is ignored. At this time the programming
sequence can start according to the flow diagram
(Fig. 12).
At first the Keyword (00111010) has to be sent to
L6280
the L6280 to activate the watch - dog function
that begins to control the microprocessor func-
tionality. From this moment the microprocessor
must send periodically the Watch-dog word
(00110101) otherwise its absence is interpreted
as a microprocessor failure: to prevent any dam-
age both in the load and in the IC, the L6280 itself
disables the power stages. No reset signal is gen-
erated towards the CPU; the system must restart
the sequence from Power-ON.
The next step is to set the configuration of chan-
nel 1 and channel 2 output stages by the initiali-
zation word. The configuration can be chosen to
fit in the load characteristics. To do this the micro-
processor generates a word with A0, A1 = 0 and
where A2, A3 choose the channel to be config-
ured, D0 to D3 choose the type of configuration
(unipolar, dual half bridge or full bridge; see Data
and Address decoding). Every input configuration
different from the allowed initialization word is ig-
nored.
When the initialization arrives, the L6280 sets the
configuration of the output stage of the chosen
channel. The initialization word has to be re-
peated for the other channel (CH1 or CH2 only). If
two initializations arrive for the same channel, the
L6280 disables the output stages while pin Reset
Out goes low for a time Td to advise the mocro-
processor about the uncorrect condition. The pro-
gram sequence must restart from the Keyword
step. After the initialization step is succesfully
completed the L6280 begins to accept com-
mands. If a command is sent before the relative
channel has been configured, the command is
neglected.
Command can be of three type:
a - selection of current level loading a DAC;
b - increment or decrement of a DAC;
c - selection of the driving strategy of a channel
(e.g. half/full step, fast/slow decay and so on).
To select the current level is necessary to load a
value into the appropriate DAC. The microproces-
sor must select the channel via A2, A3 and (only
for channel 1 and 2) left or right DAC via D3; the
value of D0,....D2 are loaded in the chosen DAC.
There are two possibilities of changing the value
of a DAC; the first one is to load directly the new
value, the second one is to cause an increment or
a decrement in a DAC, in this way the burden of
the microprocessor can be partially decreased
generating inc/dec command without calculating
the value.
To increment od decrement a DAC the microproc-
essor must select the channel via A2,A3, left or
right DAC and the operation via D0 to D3 accord-
ing to truth table in Datas and Address Decoding
(see below). The increment or decrement is done
immediately after the arrive of the command. For
every configuration of the output stages are pos-
sible different type of driving strategy explained in
Datas and Address Decoding.
11/26
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