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PDF L6712ADTR Data sheet ( Hoja de datos )
| Número de pieza | L6712ADTR | |
| Descripción | TWO-PHASE INTERLEAVED DC/DC CONTROLLER | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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L6712
L6712A
TWO-PHASE INTERLEAVED DC/DC CONTROLLER
■ 2 PHASE OPERATION WITH
SYNCHRONOUS RECTIFIER CONTROL
■ ULTRA FAST LOAD TRANSIENT RESPONSE
■ INTEGRATED HIGH CURRENT GATE
DRIVERS: UP TO 2A GATE CURRENT
■ 3 BIT PROGRAMMABLE OUTPUT FROM
0.900V TO 3.300V OR WITH EXTERNAL REF.
■ ±0.9% OUTPUT VOLTAGE ACCURACY
■ 3mA CAPABLE AVAILABLE REFERENCE
■ INTEGRATED PROGRAMMABLE REMOTE
SENSE AMPLIFIER
■ PROGRAMMABLE DROOP EFFECT
■ 10% ACTIVE CURRENT SHARING ACCURACY
■ DIGITAL 2048 STEP SOFT-START
■ CROWBAR LATCHED OVERVOLTAGE PROT.
■ NON-LATCHED UNDERVOLTAGE PROT.
■ OVERCURRENT PROTECTION REALIZED
USING THE LOWER MOSFET'S RdsON OR A
SENSE RESISTOR
■ OSCILLATOR EXTERNALLY ADJUSTABLE
AND INTERNALLY FIXED AT 150kHZ
■ POWER GOOD OUTPUT AND INHIBIT FUNCTION
■ PACKAGES: SO-28 & VFQFPN-36
APPLICATIONS
■ HIGH CURRENT DC/DC CONVERTERS
■ DISTRIBUTED POWER SUPPLY
BLOCK DIAGRAM
SO28
VFQFPN-36 (6x6x1.0)
Package
SO
VFQFPN
ORDERING NUMBERS:
Tube
Tape & Reel
L6712D, L6712AD L6712DTR, L6712ADTR
L6712Q, L6712AQ L6712QTR, L6712AQTR
DESCRIPTION
The device implements a dual-phase step-down con-
troller with a 180 phase-shift between each phase
optimized for high current DC/DC applications.
Output voltage can be programmed through the in-
tegrated DAC from 0.900V to 3.300V; program-
ming the "111" code, an external reference from
0.800V to 3.300V is used for the regulation.
Programmable Remote Sense Amplifier avoids
use of external resistor divider and recovers loss-
es along distribution line.
The device assures a fast protection against load
over current and Over / Under voltage.An internal
crowbar is provided turning on the low side mosfet
if Over-voltage is detected.
Output current is limited working in Constant Cur-
rent mode: when Under Voltage is detected, the
device resets, restarting operation.
PGOOD
BAND-GAP
REFERENCE
OSC / INH
SGND
PWM1
VCCDR
HS
BOOT1
UGATE1
PHASE1
March 2004
VID2
VID1
VID0
REF_IN/OUT
DAC
DIGITAL
SOFT-START
LOGIC AND
PROTECTIONS
VCC
VCCDR
CH1 OCP CH2 OCP
TOTAL
CURRENT
VPROG
CH1
OCP
LS
CH2
OCP
CURRENT
READING
CURRENT
READING
LS
FBG
FBR
REMOTE
AMPLIFIER
VSEN
PWM2
ERROR
AMPLIFIER
DROOP FB
COMP
Vcc
Vcc
HS
LGATE1
ISEN1
PGNDS1
PGND
PGNDS2
ISEN2
LGATE2
PHASE2
UGATE2
BOOT2
1/27
1 page  
L6712A L6712
PIN FUNCTION
N. (*)
SO VFQFPN
1 33
2 34
3 35
4 36
52
64
7 5,6
87
98
10 9
11 11
12 12
13 13
14 14
15 15
Name
LGATE1
VCCDR
PHASE1
UGATE1
BOOT1
VCC
SGND
COMP
FB
DROOP
REF_IN /
OUT
VSEN
ISEN1
PGNDS1
PGNDS2
Description
Channel 1 LS driver output.
A little series resistor helps in reducing device-dissipated power.
LS drivers supply: it can be varied from 5V to 12V buses.
Filter locally with at least 1µF ceramic cap vs. PGND.
Channel 1 HS driver return path. It must be connected to the HS1 mosfet source
and provides the return path for the HS driver of channel 1.
Channel 1 HS driver output.
A little series resistor helps in reducing device-dissipated power.
Channel 1 HS driver supply. This pin supplies the relative high side driver.
Connect through a capacitor (100nF typ.) to the PHASE1 pin and through a diode
to VCC (cathode vs. boot).
Device supply voltage. The operative supply voltage is 12V ±10%.
Filter with 1µF (Typ.) capacitor vs. GND.
All the internal references are referred to this pin. Connect it to the PCB signal
ground.
This pin is connected to the error amplifier output and is used to compensate the
control feedback loop.
This pin is connected to the error amplifier inverting input and is used to
compensate the control feedback loop.
A current proportional to the sum of the current sensed in both channel is
sourced from this pin (50µA at full load, 70µA at the Constant Current threshold).
Short to FB to implement the Droop effect: the resistor connected between FB
and VSEN (or the regulated output) allows programming the droop effect.
Otherwise, connect to GND directly or through a resistor (43kΩ max) and filter
with 1nF capacitor. In this last case, current information can be used for other
purposes.
Reference input/output. Filter vs. GND with 1nF ceramic capacitor (a total of
100nF capacitor is allowed).
It reproduces the reference used for the regulation following VID code: when
VID=111, the reference for the regulation must be connected on this pin.
References ranging from 0.800V up to 3.300V can be accepted.
Connected to the output voltage it is able to manage Over & Under-voltage
conditions and the PGOOD signal. It is internally connected with the output of the
Remote Sense Amplifier for Remote Sense of the regulated voltage.
Connecting 1nF capacitor max vs. GND can help in reducing noise injection at
this pin.
If no Remote Sense is implemented, connect it directly to the regulated voltage in
order to manage OVP, UVP and PGOOD.
Channel 1 current sense pin. The output current may be sensed across a sense
resistor or across the low-side mosfet RdsON. This pin has to be connected to the
low-side mosfet drain or to the sense resistor through a resistor Rg.
The net connecting the pin to the sense point must be routed as close as
possible to the PGNDS net in order to couple in common mode any picked-up
noise.
Channel 1 Power Ground sense pin. The net connecting the pin to the sense
point must be routed as close as possible to the ISEN1 net in order to couple in
common mode any picked-up noise.
Channel 2 Power Ground sense pin. The net connecting the pin to the sense
point must be routed as close as possible to the ISEN2 net in order to couple in
common mode any picked-up noise.
5/27
5 Page 
L6712A L6712
CURRENT READING AND OVER CURRENT
The current flowing trough each phase is read using the voltage drop across the low side mosfets RdsON
or across a sense resistor (RSENSE) in series to the LS mosfet and internally converted into a current. The
transconductance ratio is issued by the external resistor Rg placed outside the chip between ISENx and
PGNDSx pins toward the reading points. The differential current reading rejects noise and allows to place
sensing element in different locations without affecting the measurement's accuracy. The current reading
circuitry reads the current during the time in which the low-side mosfet is on (OFF Time). During this time,
the reaction keeps the pin ISENx and PGNDSx at the same voltage while during the time in which the
reading circuitry is off, an internal clamp keeps these two pins at the same voltage sinking from the ISENx
pin the necessary current (Needed if low-side mosfet RdsON sense is implemented to avoid absolute max-
imum rating overcome on ISENx pin).
The proprietary current reading circuit allows a very precise and high bandwidth reading for both positive
and negative current. This circuit reproduces the current flowing through the sensing element using a high
speed Track & Hold transconductance amplifier. In particular, it reads the current during the second half
of the OFF time reducing noise injection into the device due to the mosfet turn-on (See fig. 4-left). Track
time must be at least 200ns to make proper reading of the delivered current.
This circuit sources a constant 50µA current from the PGNDSx pin: it must be connected through the Rg
resistor to the ground side of the sensing element (See Figure 4-right). The two current reading circuitries
use this pin as a reference keeping the ISENx pin to this voltage.
The current that flows in the ISENx pin is then given by the following equation:
IISENx
=
50µA + -R----S---E----N----S----E----⋅---I--P----H----A----S---E----x-
Rg
=
50 µA + IINFOx
Where RSENSE is an external sense resistor or the RdsON of the low side mosfet and Rg is the transcon-
ductance resistor used between ISENx and PGNDSx pins toward the reading points; IPHASEx is the current
carried by the relative phase. The current information reproduced internally is represented by the second
term of the previous equation as follow:
IINFOx
=
R-----S----E---N----S----E----⋅---I--P----H----A----S---E----x-
Rg
Since the current is read in differential mode, also negative current information is kept; this allow the de-
vice to check for dangerous returning current between the two phases assuring the complete equalization
between the phase's currents. From the current information of each phase, information about the total cur-
rent delivered (IFB = IINFO1 +IINFO2) and the average current for each phase (IAVG = (IINFO1 +IINFO2)/2 ) is
taken. IINFOX is then compared to IAVG to give the correction to the PWM output in order to equalize the
current carried by the two phases.
Figure 4. Current reading timing (left) and circuit (right)
ILS1
ILS2
IFB
Track & Hold
LGATEx
ISENx
PGNDSx
Rg
IISENx
Rg
50µA
11/27
11 Page | ||
| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet L6712ADTR.PDF ] | |
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