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PDF L6926 Data sheet ( Hoja de datos )
| Número de pieza | L6926 | |
| Descripción | HIGH EFFICIENCY MONOLITHIC SYNCHRONOUS STEP DOWN REGULATOR | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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L6926D
HIGH EFFICIENCY MONOLITHIC SYNCHRONOUS
STEP DOWN REGULATOR
s 2V TO 5.5V BATTERY INPUT RANGE
s HIGH EFFICIENCY: UP TO 95%
s INTERNAL SYNCHRONOUS SWITCH
s NO EXTERNAL SCHOTTKY REQUIRED
s EXTREMELY LOW QUIESCENT CURRENT
s 1µA MAX SHUTDOWN SUPPLY CURRENT
s 800mA MAX OUTPUT CURRENT
s ADJUSTABLE OUTPUT VOLTAGE FROM 0.6V
s LOW DROP-OUT OPERATION: UP TO100%
DUTY CYCLE
s SELECTABLE LOW NOISE/LOW
CONSUMPTION MODE AT LIGHT LOAD
s POWER GOOD SIGNAL
s ±1% OUTPUT VOLTAGE ACCURACY
s CURRENT-MODE CONTROL
s 600kHz SWITCHING FREQUENCY
s EXTERNALLY SYNCHRONIZABLE FROM
500kHz TO 1.4MHz
s OVP
s SHORT CIRCUIT PROTECTION
APPLICATIONS
s BATTERY-POWERED EQUIPMENTS
s PORTABLE INSTRUMENTS
s CELLULAR PHONES
s PDAs AND HAND HELD TERMINALS
s DSC
APPLICATION TEST CIRCUIT
MSOP8
ORDERING NUMBERS: L6926D
L6926D013TR (Tape & Reel)
s GPS
DESCRIPTION
The device is dc-dc monolithic regulator specifically
designed to provide extremely high efficiency.
L6926D supply voltage can be as low as 2V allowing
its use in single Li-ion cell supplied applications. Out-
put voltage can be selected by an external divider
down to 0.6V. Duty Cycle can saturate to 100% al-
lowing low drop-out operation. The device is based
on a 600kHz fixed-frequency, current mode-architec-
ture. Low Consumption Mode operation can be se-
lected at light load conditions, allowing switching
losses to be reduced. L6926D is externally synchro-
nizable with a clock which makes it useful in noise-
sensitive applications. Other features like Power-
good, Overvoltage protection, Shortcircuit protection
and Thermal Shutdown (150°C) are also present.
VIN=2V to 5.5V
C1
10µF
6.3V
SYNC
VCC
RUN
7
6
1
2
COMP
D01IN1305
C2
220pF
L 6.8µH
5
LX
R3
500K
8
PGOOD
3
4 VFB
GND
R2
200K
R1
100K
VOUT=1.8V
C4
10µF
6.3V
May 2003
1/8
1 page  
L6926D
Low Noise Mode
If for noise reasons, the very low frequencies of the low consumption mode are undesirable, the low noise mode
can be selected. In low noise mode, the efficiency is a little bit lower compared with the low consumption mode
in very light load conditions but for medium-high load currents the efficiency values are very similar.
Basically, the device switches with its internal free running frequency of 600KHz. Obviously, in very light load
conditions, the device could skip some cycles in order to keep the output voltage in regulation.
Synchronization
The device can also be synchronized with an external signal from 500KHz up to 1.4MHz.
In this case the low noise mode is automatically selected. The device will eventually skip some cycles in very
light load conditions.
The internal synchronization circuit is inhibited in shortcircuit and overvoltage conditions in order to keep the
protections effective (see relative sections).
Short Circuit Protection
During the device operation, the inductor current increases during the high side turn on phase and decrease
during the high side turn off phase based on the following equations:
∆ ION
=
(---V----I--N-----–----V----O----U----T----)
L
⋅
TON
∆IOFF
=
(---V----O----U----T---)-
L
⋅
TOFF
In strong overcurrent or shortcircuit conditions the VOUT can be very close to zero. In this case ∆ION increases
and ∆IOFF decreases. When the inductor peak current reaches the current limit, the high side mosfet turns off
and so the TON is reduced down to the minimum value (250ns typ.) in order to reduce as much as possible ∆ION.
Anyway, if VOUT is low enough it can be that the inductor peak current further increases because during the
TOFF the current decays very slowly.
Due to this reason a second protection that fixes the maximum inductor valley current has been introduced. This
protection doesn't allow the high side MOSFET to turn on if the current flowing through the inductor is higher
that a specified threshold (valley current limit). Basically the TOFF is increased as much as required to bring the
inductor current down to this threshold.
So, the maximum peak current in worst case conditions will be:
IPEAK
=
IV A L L E Y
+
-V---I--N--
L
⋅
T O N _MIN
Where IPEAK is the valley current limit (1.4A typ.) and TON_MIN is the minimum TON of the high side MOSFET.
Slope Compensation
In current mode architectures, when the duty cycle of the application is higher than approximately 50%, a pulse-
by-pulse instability (the so called sub harmonic oscillation) can occur.
To allow loop stability also in these conditions a slope compensation is present. This is realized by reducing the
current flowing through the inductor necessary to trigger the COMP comparator (with a fixed value for the COMP
pin voltage).
With a given duty cycle higher than 50%, the stability problem is particularly present with an higher input voltage
(due to the increased current ripple across the inductor), so the slope compensation effect increases as the input
voltage increases.
5/8
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet L6926.PDF ] | |
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