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PDF STA8088FG Data sheet ( Hoja de datos )
| Número de pieza | STA8088FG | |
| Descripción | Fully Integrated GPS/Galileo/Glonass/QZSS Receiver | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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STA8088FG
Fully Integrated GPS/Galileo/Glonass/QZSS Receiver
with embedded RF and in-package Flash
Data brief preliminary data
Features
■ STMicroelectronics® 3rd generation positioning
receiver with 32 Tracking channels and 2 fast
acquisition channels compatible with GPS,
Galileo and Glonass systems
■ Embedded RF Front-End with separate
GPS/Galieo/QZSS and Glonass IF outputs
■ Embedded low noise amplifier
■ -162 dBm indoor sensitivity (tracking mode)
■ Fast TTFF < 1 s in Hot start and 35 s in Cold
Start
■ High performance ARM946 MCU (up to
208 MHz)
■ 256 Kbyte embedded SRAM
■ In-Package SQI Flash Memory (16 Mbits)
■ Real Time Clock (RTC) circuit
■ 32-bit Watch-dog timer
■ 3 UARTs
■ 1 I2C master/slave interface
■ 1 Synchronous Serial Port (SSP, Motorola-SPI
supported) or 1 External SQI Flash interface
■ USB2.0 dual-role full speed (12 MHz) with
integrated physical layer transceiver
■ 2 Controller Area Network (CAN)
■ 2 channels ADC (10 bits)
■ 3 Embedded 1.8 V voltage regulators
■ I/O level selectable 1.8 V or 3.3 V
■ Operating Condition:
– VDD12: 1.2 V ±10%
– VDD18/RF18: 1.8 V ±5%
– VLPVR 1.62 V to 3.6 V
– VddIO: 1.8 V ±5%; 3.3 V ±10%
VFQFPN56
(7x7x0.85mm)
■ Package:
– VFQFPN56 (7 x 7 x 0.85 mm) 0.4 mm
pitch
■ Ambient temperature range: -40/+85°C
Description
STA8088FG is a single die standalone positioning
receiver IC working on multiple constellations
(GPS/Galileo/Glonass/QZSS).
The minimum BOM make STA8088FG the ideal
solution for low-cost and small footprint products
such handheld computers, cameras, data
loggers, and sports accessories.
The device is offered with a complete GNSS
firmware which performs all GNSS operations
including tracking, acquisition, navigation and
data output with no need of external memories
September 2013
Doc ID 022731 Rev 3
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice. For further information contact your local STMicroelectronics sales office.
1/17
www.st.com
1
1 page  
STA8088FG
1 Overview
Overview
STA8088FG is a highly integrated System-On-Chip device designed for positioning systems
applications.
The low power consumption and minimum BOM make STA8088FG the ideal solution for
low-cost and battery-operated portable products such handheld, computers, cameras, data
loggers and sports accessories, as well as automotive application.
It combines a high performance ARM946 microprocessor with embedded enhanced
peripherals and I/O capabilities with ST next generation triple-constellation positioning
engine. The RF front-end and base band processor are able to support GPS/Galileo and
Glonass navigation systems. The device is offered with a complete firmware which performs
all positioning operations including tracking, acquisition, navigation and data output with no
need of external memories.
It also provides clock generation via PLL, backup logic with real time clock and it supports
USB2.0 standard at full speed, (12 Mbps) with on-chip PHY.
STA8088FG is software compatible with the ARM processor family. The device is power
supplied with 1.8V and uses three on-chip voltage regulators to internally supply the RF
front-end, core logic and the backup logic. In order to reduce the power consumption the
chip can be directly powered with 1.2 V bypassing the embedded voltage regulators which
will be put in power down mode.
I/O lines are compatible with 1.8 V and 3.3 V.
The chip, using STMicroelectronics CMOSRF Technology, is housed in a VFQFPN-56
(7 x 7 x 0.85 mm) package with stacked 16 Mbit Flash memory.
Doc ID 022731 Rev 3
5/17
5 Page 
STA8088FG
Pin description
Table 5. Port 0 pins
Symbol I/O voltage I/O
Mode
Functions
IO Default GPIO.0: General Purpose IO
P0.0
VDD_IOR1
I
O
A PPS_IN: Pulse Per Second Input
B PPS_OUT: Pulse Per Second Output
O C SSP_CSN: SSP Chip Select Active Low
O Default CAN1TX(1): CAN1 Transmit Data Output
P0.8 VDD_IOR5 IO
A GPIO.8: General Purpose IO
IO B I2C_SD: I2C Serial Data
I Default CAN1RX(1): CAN 1 Receive Data Input
P0.9 VDD_IOR5 IO
A GPIO.9: General Purpose IO
O B I2C_SCLK: I2C Clock
1. Only for STA8088FGB (see Figure 5: Ordering information scheme).
VFQFPN56
35
55
1
2.8 Port 1 pins
Port 1 consists of a 32-bit bidirectional I/O port (only9-bit are used in STA8088FG).
It can be either used as general purpose Input or Output port, or configured according to the
associated alternate functions.
Table 6.
Symbol
Port 1 pins
I/O Voltage
P1.0
VDD_IOR1
P1.1
VDD_IOR1
P1.2
VDD_IOR1
I/O Mode
Functions
O
Default
SSP_CSN/IOPWRSEL_R1: SSP chip select active
low / I/O Ring 1 power selection
I/O A GPIO32: general purpose I/O
I/O B SIGNGGPS: GGPS 3-bit coding output (sign)
O C SQI_CEN: SQI Flash chip enable
I/O Default SSP_CLK: SSP clock
I/O A GPIO33: general purpose I/O
I/O B CLOCK_GGPS: GGPS clock out
O C SQI_CLK: SQI Flash clock
I Default SSP_DI: SSP serial data input
I/O A GPIO34: general purpose I/O
I/O B SIGNGNS: GNS 3-bit coding output (sign)
IO C SQI_SIO0/SI: SQI Flash data I/O 0 / serial I
VFQFPN56
40
41
42
Doc ID 022731 Rev 3
11/17
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet STA8088FG.PDF ] | |
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