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PDF MG87FL52 Data sheet ( Hoja de datos )
| Número de pieza | MG87FL52 | |
| Descripción | Single-chip 8 bits microcontroller | |
| Fabricantes | Megawin Technology | |
| Logotipo |  |
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Megawin Technology Co., Ltd.
MG87FE/L52
1.0 General Description
MG87FE/L52 is a single-chip 8 bits microcontroller with the instruction sets fully compatible
with industrial-standard 80C51 series microcontroller. 8K bytes flash memory and 256 bytes
RAM has been embedded to provide wide field application. In-System-Programming and
In-Application-Programming allow the users to download new code or data while the
microcontroller sits in the application. This device executes one machine cycle in 6 clock or 12
clock cycles. MG87FE/L52 has four 8-bit I/O ports, one 4-bit I/O ports, three 16-bit
timer/counters, an eight-source, four-priority-level interrupt structure, an enhanced UART,
on-chip crystal oscillator.
Excellent flash-endurance, flash-retention, and code-protecting security make MG87FE/L52 as
an excellent micro-controller.
2.0 Features
z 80C51 Central Processing Unit
z 8KB On-Chip program memory for program ROM, ISP ROM & IAP zone.
z ISP capability; optional 0.5K/1KB/1.5K~3.5KB ISP memory shared with 8KB flash memory.
z IAP capability; program controlled IAP memory size shared with 8KB flash memory.
z On-Chip 256 bytes scratch-pad RAM. Also, the MCU can address up to 64K bytes external
memory.
z MOVC-disabling, encrypting, and locking flash memory realize security mechanism.
z Three 16-bits timer/counter, Timer2 is an up/down counter with programmable clock output
on P1.0
z Eight sources, four-level-priority interrupt capability
z Enhanced UART, provides frame-error detection and hardware address-recognition
z Dual DPTR for fast-accessing of data memory
z 15 bits Watch-Dog-Timer with 8-bits pre-scaler, one-time enabled
z Low EMI: inhibits ALE emission
z Power control: Idle mode and Power-Down mode; Power-Down can be woken-up by
P3.2/P3.3/P4.2/P4.3, Idle mode could be woken up by all interrupt sources.
z I/O port: 32+4 I/O ports :
- PDIP-40 (MG87FE/L52AE or MG87FE/L52GE) has 32 I/O ports;
Preliminary ver 1.3 Date: 2009-JAN-20 1
1 page  
Megawin Technology Co., Ltd.
MG87FE/L52
P3.0 (RXD)
P3.1 (TXD)
P3.2 (INT0)
P3.3 (INT1)
P3.4 (T0)
P3.5 (T1)
P3.6 (/WR)
P3.7 (/RD)
10
11
12
13
14
15
16
17
11
13
14
15
16
17
18
19
P4.0
P4.1
P4.2 (/INT3)
P4.3 (/INT2)
RESET
9
ALE 30
23
34
1
12
10
33
/PSEN
/EA
29 32
31 35
XTAL1
XTAL2
19 21
18 20
5 I/O Port 3 is an 8-bit bidirectional I/O port
7 with internal pull-ups and can be used
8 as inputs. Port 3 pins that have 1s
written to them are pulled high by the
9
internal pull-ups and can be used as
10 inputs. As inputs, port 3 pins that are
11 externally pulled low will source current
12 because of the internal pull-ups. Port3
13 also serves other special functions of
this device.
P3.0 and P3.1 act as receiver and
transceiver of the data for UART
function block, Alias RXD and TXD.
P3.2 and P3.3 also act as external
interrupt sources, alias INT0 and INT1.
P3.4 and P3.5 also act as event
sources for timer0 and timer1
individually, alias T0 and T1.
P3.6 also acts as write signal while
access to external memory, alias /WR.
P3.7 also acts as read signal while
access to external memory, alias /RD.
17 I/O Port4 is extended I/O ports such like
28 Port1. It can be available only on
39 44L-PLCC and 44L-PQFP package.
6 P4.2 and P4.3 also act as external
interrupt sources, alias INT3 and INT2.
4 I A high on this pin for at least two
machine cycles will reset the device.
27 O Output pulse for latching the low bytes
of address during accesses to external
memory.
26 O The read strobe to external program
memory, low active.
29 I /EA must be kept at low to enable the
device to fetch program code from
external flash memory.
An internal pull-up resistor has been
embedded in this pin.
15 I Input to the inverting oscillator
amplifier.
14 O Output from the inverting amplifier.
Preliminary ver 1.3 Date: 2009-JAN-20 5
5 Page 
Megawin Technology Co., Ltd.
MG87FE/L52
7.2 Option setting:
LOCK
ROM code lock-option. When read ROM code & always get 0xFF, PAGE-
ERASE and PROGRAM is also disabled.
SB When enabled, dump ROM code & the data will be scrambled.
MOVCL When enabled, the MOVC operation will be disabled at external mode.
HWBS When power-up, MCU will boot from ISP-memory if ISP-memory is configured.
HWBS2
In addition to power-up, the reset from RESET-pin will also force MCU to boot
from ISP-memory if ISP-memory is configured.
EN6T MCU 6T/12T mode, MCU will work at 6T mode when this option was enabled.
OSCDN
The gain of oscillator driving capability. Enable this option could help to reduce
EMI and cause the lower power consumption. *note-1
FZWDTCR
When enabled, The WDTCR register will be initialized to its reset value only by
power-on reset.
Note-1: When OSCDN option was enabled, the power consumption could be lower.
7.3 Data RAM Addressing
MG87FE/L52 has internal data RAM that is mapped to three separated segments. The lower
128 bytes of RAM, upper 128 bytes of RAM and 128 bytes Special Function Register(SFR).
Lower 128 bytes of RAM: (addresses 0x00 to 0x7F) are accessed by either direct or indirect
addressing. Upper 128 bytes of RAM: (addresses 0x80 to 0xFF) are accessed only by indirect
addressing (using R0 or R1). The Special Function Registers: (addresses 0x80 to 0xFF) are
accessed only by direct addressing.
While the program counter is spanning over 1FFFh, the device will fetch its program code from
the external memory at once ignoring the /EA pin status. In that case, it will never fetch the
program code from the following embedded flash.
Preliminary ver 1.3 Date: 2009-JAN-20 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MG87FL52.PDF ] | |
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