|
|
PDF L6996 Data sheet ( Hoja de datos )
| Número de pieza | L6996 | |
| Descripción | DINAMICALLY PROGRAMMABLE SYNCHRONOUS STEP DOWN CONTROLLER FOR MOBILE CPUs | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de L6996 (archivo pdf) en la parte inferior de esta página. Total 26 Páginas | ||
|
No Preview Available !
L6996
DINAMICALLY PROGRAMMABLE SYNCHRONOUS
STEP DOWN CONTROLLER FOR MOBILE CPUs
s 5 BIT DAC WITH AVAILABLE EXTERNAL
OUTPUT VOLTAGE.
s 0.6 TO 1.750V, DYNAMICALLY ADJUSTABLE
OUTPUT VOLTAGE RANGE.
s ±1% OUTPUT ACCURACY OVER LINE AND LOAD.
s ACTIVE DROOP.
s CONSTANT ON TIME TOPOLOGY ALLOWS
LOW DUTY CYCLE AND FAST LOAD
TRANSIENT.
s 90% EFFICIENCY FROM 12V TO 1.35V/8A.
s 1.750V TO 28V BATTERY INPUT RANGE.
s OPERATING FREQUENCY UP TO 1MHZ.
s INTEGRATED HIGH CURRENT DRIVERS.
s LATCHED OVP AND UVP PROTECTIONS.
OCP PROTECTION.
s 350µA TYP. QUIESCENT CURRENT.
s 7µA TYP. SHUTDOWN SUPPLY CURRENT.
s PGOOD AND OVP SIGNALS.
s ZERO-CURRENT DETECTION AND PULSE-
FREQUENCY MODE.
APPLICATIONS
s ADVANCED MOBILE CPUs SUPPLY WITH
DYNAMIC TRANSITIONS.
s NOTEBOOK/LAPTOP, CONCEPT PC CPUs
SUPPLY.
s DC/DC FROM BATTERY SUPPLY EQUIPMENTS.
APPLICATION DIAGRAM
5V
TSSOP24
ORDERING NUMBERS: L6996D (TSSOP24)
L6996DTR (Tape & Reel)
DESCRIPTION
The device is dc-dc controller specifically designed to
provide extremely high efficiency conversion for mo-
bile advanced microprocessors.
The "constant on-time" topology assures fast load
transient response. The embedded "voltage feedfor-
ward" provides nearly constant switching frequency
operation.
A precise 5-bit DAC allows select output voltage from
0.6V to 1V with 25mV steps and from 1V to 1.75V
with 50mV steps.
L6996 is capable of supporting CPUs VID combina-
tion changing during normal operation.
The active droop allows adjust both the output load-
line slope and the zero-load output voltage.
25V
July 2002
OSC
BOOT
HGATE
PGOOD
PHASE
OVP
LGATE
L6996
ILIM
PGND
GND
CS+
CS-
CSS
SS
VFB-
VFB+
HS
LS
DS
5V
L RSENSE VOUT
1.25V
SHDN
VID4:0
VPROG
CVPROG
1/26
1 page  
ELECTRICAL CHARACTERISTICS (continued)
(VCC = VDR = 5V; Tamb = 0°C to 70°C unless otherwise specified)
Symbol
Parameter
Test Condition
UVP Under voltage trip
CS- falling
PGOOD Upper threshold
(CS-/VPROG)
CS- rising; PGOOD active
PGOOD Lower threshold
(CS-/VPROG)
CS- falling; PGOOD active
Ron
PGOOD
ISOURCE=2mA
Table 1. DAC Output Voltage
VID4
VID3
11
11
11
11
11
11
11
11
10
10
10
10
10
10
10
10
01
01
01
01
01
01
01
01
00
00
00
00
00
00
00
00
VID2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
VID1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
VID0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
L6996
Min.
66
109
Typ.
69
112
Max.
72
115
Unit
%
%
84 87 90 %
40 60 100 Ω
Output Voltage (V)
0.600
0.625
0.650
0.675
0.700
0.725
0.750
0.775
0.800
0.825
0.850
0.875
0.900
0.925
0.950
0.975
1.000
1.050
1.100
1.150
1.200
1.250
1.300
1.350
1.400
1.450
1.500
1.550
1.600
1.650
1.700
1.750
5/26
5 Page 
L6996
conditions are met contemporarily: the PWM comparator output is low (i.e. the output voltage is below the ref-
erence voltage), the minimum off time is passed and the current limit comparator is not triggered (i.e. the induc-
tor current is under the current limit programmed value). The voltage on the OSC pin must range between 50mV
and 2V to ensure the system linearity.
1.2 Closing the loop
The loop is closed connecting the output voltage to the FB- pin. The FB- pin is linked internally to the comparator
negative pin and the positive pin is connected to the programmed voltage as in Figure 12. When the FB- goes
lower than FB+, the PWM comparator output goes high and sets the flip-flop output, turning on the high side
MOSFET. This condition is latched to avoid noise spike. After the on-time (calculated as described in the pre-
vious section) the system resets the flip-flop and then turns off the high side MOSFET and turns on the low side
MOSFET. Internally the device has more complex logic than a flip-flop to manage the transition in correct way.
For more details refers to the schematic Fig. 1. Because the system implements a valley loop control, the aver-
age output voltage is different from the programmed one as shown in figure 13.
Figure 13. Valley Regulation
Vout
DC Error Offset
<Vout>
Vref
Figure 14. Voltage positioning network
Time
To inductor Rsense
PWM
COMPARATOR
- VFB-
R4
R1
+
VFB+ R2
To Vout
R3
L6996 Vprog
The L6996 performs an externally adjustable active droop, achieving a 4m V/A load line slope using a 1.5mΩ
sense resistor without use an external amplifier. Focusing the attention on the control part of the system (Figure
14), it can be considered that the inductor current can revert (the PFM function is deal towards) and the current
11/26
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet L6996.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| L6995 | STEP DOWN CONTROLLER FOR HIGH DIFFERENTIAL INPUT-OUTPUT CONVERSION | STMicroelectronics |
| L6995D | STEP DOWN CONTROLLER FOR HIGH DIFFERENTIAL INPUT-OUTPUT CONVERSION | STMicroelectronics |
| L6995DTR | STEP DOWN CONTROLLER FOR HIGH DIFFERENTIAL INPUT-OUTPUT CONVERSION | STMicroelectronics |
| L6996 | DINAMICALLY PROGRAMMABLE SYNCHRONOUS STEP DOWN CONTROLLER FOR MOBILE CPUs | STMicroelectronics |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |