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PDF 74HC164 Data sheet ( Hoja de datos )

Número de pieza 74HC164
Descripción 8 bit String into and out of the shift register
Fabricantes FUMAN ELECTRONICS 
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No Preview Available ! 74HC164 Hoja de datos, Descripción, Manual

深圳市富满电子有限公司
SHENZHEN FUMAN ELECTRONICS CO., LTD.
54HC164/74HC164(文件编号:S&CIC0464)
AND-Gated (Enable/Disable) Serial Inputs
Fully Buffered Clock and Serial Inputs
Direct Clear
Package Options Include Plastic
Small-Outline (D) and Ceramic Flat (W)
Packages, Ceramic Chip Carriers (FK), and
Standard Plastic (N) and Ceramic (J)
300-mil DIPS
8 bit 串入并出移位寄存器
DESCRIPTION
These 8-bit shift registers feature AND-gated serial inputs and an asynchronous clear (CLR) input. The gated
serial (A and B) inputs permit complete control over incoming data; a low at either input inhibits entry of the new
data and resets the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input enables the other
input, which then determines the state of the f1irst flip-flop. Data at the serial inputs can be ch2anged while CLK is
high or low, provided the minimum setup time requirements are met. Clocking occurs on the low-to-high-level
transition of CLK.
The 54HC164 is characterized for operation over the full military temperature range of 55to 125. The
123
74HC164 is characterized for operation from -40to 85. 1
2
54HC164…J OR W PACKAGE
54HC164…FK PACKAGE (TOP VIEW)
74HC164…D OR N PACDKAGE
A1
14 VDD
B2
13 QH
D
QA 3
12 QG
QB 4
11 QF
QC 5
QD 6
10 QE
9 CLEAR
D
3 2 1 20 19
QA 4
18 QG
NC 5
17 NC
QB 6
16 QF
NC 7
15 NC
QC 8
14 QE
9 10 11 12 13
GND 7
8 CLOCK
FUNCTION TABLE
NC-NO internal connection
INPUTS
OUTPUTS
CLR CLK A B QA QB...QH
C L X X X LLL
H L X X QA0 QB0 QH0
H C H H H QAn QGn
H L X L QAn QGn
H X L L QAn QGn
C
QA0,QBO,QH0=the level of QA,QB,or QH,
respectively,before the indicated
steady-state input conditions were
established
QAn,QGn=the level of QA or QG before
the most recent transition of
CLK:indicates a 1-bit shift
B 1页共7
B

1 page




74HC164 pdf
深圳市富满电子有限公司
SHENZHEN FUMAN ELECTRONICS CO., LTD.
54HC164/74HC164(文件编号:S&CIC0464)
8 bit 串入并出移位寄存器
Timing requirements over recommended operating free-air temperature range (unless otherwise noted)
TA=25
54HC164
74HC164
VCC
UNIT
MIN MAX MIN MAX MIN MAX
fclock Clock frequency
2V 0 6 0 4.2 0 5
4.5V 0 31 0 21 0 25 MHz
6V 0 36 0 25 0 28
tW Pulse duration
CLR low
2V 100 - 150 - 125 -
4.5V 20 - 30 - 25 -
6V
CLK high or low 2V
17
80
- 25 - 21 -
- 120 - 100 -
ns
4.5V 16 - 24 - 20 -
6V 14 - 20 - 18 -
Date 2V 100 - 150 - 125 -
tsu Setup time before CLK
4.5V 20 - 30 - 25 -
6V 17 - 25 - 21 -
CLR inactive 2V 100 - 150 - 125 -
ns
4.5V 20 - 30 - 25 -
6V 17 - 25 - 21 -
2V 5 - 5 - 5 -
th Hold time, data after CLK
4.5V 5 - 5 - 5 - ns
6V 5 - 5 - 5 -
Switching characteristics over recommended operating free-air temperature rang, CL=50pF
(unless otherwise noted) (see Figure 1)
FROM
TO
PARAMETER
(INPUT) (OUTPUT)
VCC
TA=25
54HC164
74HC164
UNIT
MIN TYP MAX MIN MAX MIN MAX
2V 6 10 - 4.2 - 5 -
fmax 4.5V 31 54 - 21 - 25 - MHz
6V 36 62 - 25 - 28 -
2V - 140 205 - 295 - 255
tPHL
CLR Any Q
4.5V - 28 41 - 59 - 51
6V - 24 35 - 51 - 46
ns
2V - 115 175 - 265 - 220
tpd
CLK
Any Q
4.5V - 23 35 - 53 - 44
6V - 20 30 - 45 - 38
2V - 38 75 - 110 - 95
tt 4.5V - 8 15 - 22 - 19 ns
6V - 6 13 - 19 - 16
5页共7

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