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PDF DM74LS90 Data sheet ( Hoja de datos )
| Número de pieza | DM74LS90 | |
| Descripción | Decade and Binary Counters | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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March 1998
DM74LS90/DM74LS93
Decade and Binary Counters
General Description
Each of these monolithic counters contains four
master-slave flip-flops and additional gating to provide a
divide-by-two counter and a three-stage binary counter for
which the count cycle length is divide-by-five for the ’LS90
and divide-by-eight for the ’LS93.
All of these counters have a gated zero reset and the LS90
also has gated set-to-nine inputs for use in BCD nine’s
complement applications.
To use their maximum count length (decade or four bit bi-
nary), the B input is connected to the QA output. The input
count pulses are applied to input A and the outputs are as
described in the appropriate truth table. A symmetrical
divide-by-ten count can be obtained from the ’LS90 counters
by connecting the QD output to the A input and applying the
input count to the B input which gives a divide-by-ten square
wave at output QA.
Features
n Typical power dissipation 45 mW
n Count frequency 42 MHz
Connection Diagrams (Dual-In-Line Packages)
DS006381-1
Order Number DM74LS90M or DM74LS90N
See Package Number M14A or N14A
DS006381-2
Order Number DM74LS93M or DM74LS93N
See Package Number M14A or N14A
© 1998 Fairchild Semiconductor Corporation DS006381
www.fairchildsemi.com
1 page  
’LS93 Switching Characteristics
at VCC = 5V and TA = 25˚C
From (Input)
Symbol
Parameter
To (Output)
fMAX
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPHL
Maximum Clock
Frequency
Propagation Delay Time
Low to High Level Output
Propagation Delay Time
High to Low Level Output
Propagation Delay Time
Low to High Level Output
Propagation Delay Time
High to Low Level Output
Propagation Delay Time
Low to High Level Output
Propagation Delay Time
High to Low Level Output
Propagation Delay Time
Low to High Level Output
Propagation Delay Time
High to Low Level Output
Propagation Delay Time
Low to High Level Output
Propagation Delay Time
High to Low Level Output
Propagation Delay Time
High to Low Level Output
A to QA
B to QB
A to QA
A to QA
A to QD
A to QD
B to QB
B to QB
B to QC
B to QC
B to QD
B to QD
SET-0 to
Any Q
RL = 2 kΩ
CL = 15 pF
CL = 50 pF
Min Max Min Max
32 20
16 10
16 20
18 24
70 85
70 90
16 23
21 30
32 37
35 44
51 60
51 70
40 52
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5 www.fairchildsemi.com
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet DM74LS90.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| DM74LS90 | Decade and Binary Counters |  National |
| DM74LS90 | Decade and Binary Counters | Fairchild Semiconductor |
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| DM74LS93 | Decade and Binary Counters | Fairchild Semiconductor |
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