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PDF MT8980D Data sheet ( Hoja de datos )
| Número de pieza | MT8980D | |
| Descripción | Digital Switch | |
| Fabricantes | Zarlink | |
| Logotipo |  |
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ISO-CMOS ST-BUS FAMILY MT8980D
Digital Switch
Features
• Zarlink ST-BUS compatible
• 8-line x 32-channel inputs
• 8-line x 32-channel outputs
• 256 ports non-blocking switch
• Single power supply (+5 V)
• Low power consumption: 30 mW Typ.
• Microprocessor-control interface
• Three-state serial outputs
ISSUE 8
Ordering Information
March 1997
MT8980DE
MT8980DP
40 Pin Plastic DIP
44 Pin PLCC
-40°C to +85°C
Description
This VLSI ISO-CMOS device is designed for
switching PCM-encoded voice or data, under
microprocessor control, in a modern digital
exchange, PBX or Central Office. It provides
simultaneous connections for up to 256 64 kbit/s
channels. Each of the eight serial inputs and outputs
consist of 32 64 kbit/s channels multiplexed to form a
2048 kbit/s ST-BUS stream. In addition, the MT8980
provides microprocessor read and write access to
individual ST-BUS channels.
STi0
STi1
STi2
STi3
STi4
STi5
STi6
STi7
Serial
to
Parallel
Converter
C4i F0i
VDD VSS
Data
Memory
Frame
Counter
Control Register
Control Interface
Output
MUX
Connection
Memory
ODE
Parallel
to
Serial
Converter
STo0
STo1
STo2
STo3
STo4
STo5
STo6
STo7
DS CS R/W A5/ DTA D7/
A0 D0
CSTo
Figure 1 - Functional Block Diagram
2-3
1 page  
MT8980D
The higher order bits come from the Control
Register, which may be written to or read from via
the Control Interface. The lower order bits come
from the address lines directly.
The Control Register also allows the chip to
broadcast messages on all ST-BUS outputs (i.e., to
put every channel into Message Mode), or to split the
memory so that reads are from the Data Memory
and writes are to the Connection Memory Low. The
Connection Memory High determines whether
individual output channels are in Message Mode,
and allows individual output channels to go into a
high-impedance state, which enables arrays of
MT8980s to be constructed. It also controls the
CSTo pin.
All ST-BUS timing is derived from the two
signals C4i and F0i.
Software Control
The address lines on the Control Interface give
access to the Control Register directly or, depending
on the contents of the Control Register, to the High
or Low sections of the Connection Memory or to the
Data Memory.
If address line A5 is low, then the Control Register is
addressed regardless of the other address lines (see
Fig. 3). If A5 is high, then the address lines A4-A0
select the memory location corresponding to channel
0-31 for the memory and stream selected in the
Control Register.
The data in the Control Register consists of mode
control bits, memory select bits, and stream address
bits (see Fig. 4). The memory select bits allow the
Connection Memory High or Low or the Data
Memory to be chosen, and the stream address bits
define one of the ST-BUS input or output streams.
Bit 7 of the Control Register allows split memory
operation - reads are from the Data Memory and
writes are to the Connection Memory Low.
The other mode control bit, bit 6, puts every output
channel on every output stream into active Message
Mode; i.e., the contents of the Connection Memory
Low are output on the ST-BUS output streams once
every frame unless the ODE pin is low. In this mode
the chip behaves as if bits 2 and 0 of every
Connection Memory High location were 1,
regardless of the actual values.
Mode
Control
Bits
(unused)
Memory
Select
Bits
Stream
Address
Bits
76
5432
10
BIT NAME
DESCRIPTION
7 Split When 1, all subsequent reads are from the Data Memory and writes are to the Connection
Memory Memory Low, except when the Control Register is accessed again. When 0, the Memory
Select bits specify the memory for subsequent operations. In either case, the Stream
Address Bits select the subsection of the memory which is made available.
6 Message When 1, the contents of the Connection Memory Low are output on the Serial Output
Mode streams except when the ODE pin is low. When 0, the Connection Memory bits for each
channel determine what is output.
5 (unused)
4-3 Memory 0-0 - Not to be used
Select Bits 0-1 - Data Memory (read only from the microprocessor port)
1-0 - Connection Memory Low
1-1 - Connection Memory High
2-0 Stream The number expressed in binary notation on these bits refers to the input or output ST-BUS
Address stream which corresponds to the subsection of memory made accessible for subsequent
Bits operations.
Figure 4 - Control Register Bits
2-7
5 Page 
MT8980D
AC Electrical Characteristics† - Clock Timing (Figures 12 and 13)
Characteristics
Sym Min Typ‡ Max Units
Test Conditions
1 Clock Period*
tCLK 220 244 300
ns
2 I Clock Width High
3 N Clock Width Low
4
P
U
Clock Transition Time
5 T Frame Pulse SetupTime
6 S Frame Pulse Hold Time
tCH 95 122
tCL 110 122
tCTT 20
tFPS 20
tFPH 0.020
150
150
200
50
ns
ns
ns
ns
µs
7 Frame Pulse Width
tFPW
244
ns
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
* Contents of Connection Memory are not lost if the clock stops, however, ST-BUS outputs go into the high impedance state.
NB: Frame Pulse is repeated every 512 cycles of C4i.
C4i
F0i
BIT
CELLS
Channel 31
Bit o
Channel 0
Bit 7
Figure 12 - Frame Alignment
2.0V
C4i
0.8V
2.0V
F0i
0.8V
tCLK
tCL tCTT
tFPH
tCHL
tFPS
tCTT
tFPH
tFPW
Figure 13 - Clock Timing
tCH
tFPS
2-13
11 Page | ||
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