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기능 1Gb R-die DDR2 SDRAM
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K4T1G084QR 데이터시트, 핀배열, 회로
K4T1G084QR
DDR2 SDRAM
1Gb R-die DDR2 SDRAM Specification
60FBGA with Lead-Free & Halogen-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure couldresult in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
www.BDTIC.1cofo42 m/SAMSUNG Rev. 1.1 July 2008




K4T1G084QR pdf, 반도체, 판매, 대치품
K4T1G084QR
1.0 Ordering Information
Org.
128Mx8
DDR2-800 6-6-6
K4T1G084QR-HCF7
DDR2-667 5-5-5
K4T1G084QR-HCE6
Note :
1. Speed bin is in order of CL-tRCD-tRP.
2. RoHS Compliant.
3. “H” of Part number(12th digit) stand for Lead-free, Halogen-free and RoHS compliant products.
Package
60 FBGA
DDR2 SDRAM
2.0 Key Features
Speed
CAS Latency
tRCD(min)
tRP(min)
tRC(min)
DDR2-800 6-6-6
6
15
15
60
DDR2-667 5-5-5
5
15
15
60
Units
tCK
ns
ns
ns
• JEDEC standard 1.8V ± 0.1V Power Supply
• VDDQ = 1.8V ± 0.1V
• 333MHz fCK for 667Mb/sec/pin, 400MHz fCK for 800Mb/sec/
pin
• 8 Banks
• Posted CAS
• Programmable CAS Latency: 3, 4, 5, 6
• Programmable Additive Latency: 0, 1, 2, 3, 4, 5
• Write Latency(WL) = Read Latency(RL) -1
• Burst Length: 4 , 8(Interleave/nibble sequential)
• Programmable Sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended data-
strobe is an optional feature)
• Off-Chip Driver(OCD) Impedance Adjustment
• On Die Termination
• Special Function Support
- PASR(Partial Array Self Refresh)
- 50ohm ODT
- High Temperature Self-Refresh rate enable
The 1Gb DDR2 SDRAM is organized as a 16Mbit x 8 I/Os x
8banks device. This synchronous device achieves high speed
double-data-rate transfer rates of up to 800Mb/sec/pin (DDR2-
800) for general applications.
The chip is designed to comply with the following key DDR2
SDRAM features such as posted CAS with additive latency, write
latency = read latency - 1, Off-Chip Driver(OCD) impedance
adjustment and On Die Termination.
All of the control and address inputs are synchronized with a pair
of externally supplied differential clocks. Inputs are latched at the
crosspoint of differential clocks (CK rising and CK falling). All I/Os
are synchronized with a pair of bidirectional strobes (DQS and
DQS) in a source synchronous fashion. The address bus is used
to convey row, column, and bank address information in a RAS/
CAS multiplexing style. For example, 1Gb(x8) device receive 14/
10/3 addressing.
The 1Gb DDR2 device operates with a single 1.8V ± 0.1V power
supply and 1.8V ± 0.1V VDDQ.
The 1Gb DDR2 device is available in 60ball FBGAs(x8).
Note : The functionality described and the timing specifications included in
this data sheet are for the DLL Enabled mode of operation.
• Average Refresh Period 7.8us at lower than TCASE 85°C,
3.9us at 85°C < TCASE < 95 °C
• All of products are Lead-free, Halogen-free, and RoHS com-
pliant
Note : This data sheet is an abstract of full DDR2 specification and does not cover the common features which are described in “DDR2 SDRAM Device
Operation & Timing Diagram”.
www.BDTIC.4cofo42 m/SAMSUNG Rev. 1.1 July 2008

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K4T1G084QR 전자부품, 판매, 대치품
K4T1G084QR
DDR2 SDRAM
4.0 Input/Output Functional Description
Symbol
CK, CK
CKE
CS
ODT
RAS, CAS, WE
DM
BA0 - BA2
A0 - A13
DQ
DQS, (DQS)
(LDQS), (LDQS)
(UDQS), (UDQS)
(RDQS), (RDQS)
NC
VDD/VDDQ
VSS/VSSQ
VDDL
VSSDL
VREF
Type
Function
Input
Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the
positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both
directions of crossing).
Input
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and out-
put drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all banks idle), or Active
Power-Down (row Active in any bank). CKE is synchronous for power down entry and exit, and for self refresh entry.
CKE is asynchronous for self refresh exit. After VREF has become stable during the power on and initialization
swquence, it must be maintained for proper operation of the CKE receiver. For proper self-refresh entry and exit, VREF
must be maintained to this input. CKE must be maintained high throughout read and write accesses. Input buffers,
excluding CK, CK, ODT and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during
self refresh.
Input
Chip Select: All commands are masked when CS is registered HIGH. CS provides for external Rank selection on sys-
tems with multiple Ranks. CS is considered part of the command code.
Input
On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When
enabled, ODT is only applied to each DQ, DQS, DQS, RDQS, RDQS, and DM signal for x4/x8 configurations. For x16
configuration ODT is applied to each DQ, UDQS/UDQS, LDQS/LDQS, UDM, and LDM signal. The ODT pin will be
ignored if the Extended Mode Register (EMRS(1)) is programmed to disable ODT.
Input Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.
Input
Input
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coinci-
dent with that input data during a Write access. DM is sampled on both edges of DQS. Although DM pins are input only,
the DM loading matches the DQ and DQS loading. For x8 device, the function of DM or RDQS/RDQS is enabled by
EMRS command.
Bank Address Inputs: BA0, BA1 and BA2 define to which bank an Active, Read, Write or Precharge command is
being applied. Bank address also determines if the mode register or extended mode register is to be accessed during
a MRS or EMRS cycle.
Input
Address Inputs: Provided the row address for Active commands and the column address and Auto Precharge bit for
Read/Write commands to select one location out of the memory array in the respective bank. A10 is sampled during a
Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If
only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the op-code dur-
ing Mode Register Set commands.
Input/Out-
put
Data Input/ Output: Bi-directional data bus.
Input
/Output
Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered in write data. For the
x16, LDQS corresponds to the data on DQ0-DQ7; UDQS corresponds to the data on DQ8-DQ15. For the x8, an RDQS
option using DM pin can be enabled via the EMRS(1) to simplify read timing. The data strobes DQS, LDQS, UDQS,
and RDQS may be used in single ended mode or paired with optional complementary signals DQS, LDQS, UDQS, and
RDQS to provide differential pair signaling to the system during both reads and writes. An EMRS(1) control bit enables
or disables all complementary data strobe signals.
In this data sheet, "differential DQS signals" refers to any of the following with A10 = 0 of EMRS(1)
x4 DQS/DQS
x8 DQS/DQS if EMRS(1)[A11] = 0
x8 DQS/DQS, RDQS/RDQS,
if EMRS(1)[A11] = 1
x16 LDQS/LDQS and UDQS/UDQS
"single-ended DQS signals" refers to any of the following with A10 = 1 of EMRS(1)
x4 DQS
x8 DQS if EMRS(1)[A11] = 0
x8 DQS, RDQS, if EMRS(1)[A11] = 1
x16 LDQS and UDQS
No Connect: No internal electrical connection is present.
Supply Power Supply: 1.8V +/- 0.1V, DQ Power Supply: 1.8V +/- 0.1V
Supply Ground, DQ Ground
Supply DLL Power Supply: 1.8V +/- 0.1V
Supply DLL Ground
Supply Reference voltage
www.BDTIC.7cofo42 m/SAMSUNG Rev. 1.1 July 2008

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