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PDF QD14XL20 Data sheet ( Hoja de datos )
| Número de pieza | QD14XL20 | |
| Descripción | TFT LCD Module | |
| Fabricantes | Quanta | |
| Logotipo |  |
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Quanta Display Inc.
Final
Specification
Quanta Display Inc.
SPECIFICATION
QD14XL2005 1 / 26
Doc No. QD14XL20-05
Doc. REV.: 06
Issue Date: 08/08/2005
RoHS compliant
Specification for TFT LCD Module
Model No.
QD14XL20 Rev.05
□ Approved By
HP
ODM
Quanta Display Inc.
1 page  
Quanta Display Inc.
QD14XL2005 5 / 26
4. Input Terminals
4-1. TFT-LCD panel driving
CN1 (1 channel, LVDS signals – NSC/Ti standard and +3.3V DC power supply)
Using connector: FI-XB30SL-HFxx/FI-X30Sx-HFxx (JAE) or equivalent.
Interface Cable Pin Assignments
PIN NO . SYMBOL
FUNCTION
1 VSS
Ground
2 VDD
Power Supply, 3.3 V (typical)
3 VDD
Power Supply, 3.3 V (typical)
4
V EEDID
DDC 3.3V power
5 NC
Reserved for supplier test point
6
Clk EEDID
DDC Clock
7
DATA EEDID
DDC Data
8 Rin0-
- LVDS differential data input (R0-R5, G0) (odd pixels)
9 Rin0+
+ LVDS differential data input (R0-R5, G0) (odd pixels)
10 VSS
Ground
11
Odd_Rin1-
- LVDS differential data input (G1-G5, B0-B1) (odd pixels)
12 Rin1+
+ LVDS differential data input (G1-G5, B0-B1) (odd pixels)
13 VSS
Ground
14 Rin2-
- LVDS differential data input (B2-B5, HS, VS, DE) (odd pixels)
15 Rin2+
+ LVDS differential data input (B2-B5, HS, VS, DE) (odd pixels)
16 VSS
Ground
17 ClkIN-
- LVDS differential clock input (odd pixels)
18 ClkIN+
+ LVDS differential clock input (odd pixels)
19 VSS
Ground
20 NC
No connect
21 NC
No connect
22 NC
No connect
23 NC
No connect
24 NC
No connect
25 NC
No connect
26 NC
No connect
27 NC
No connect
28 NC
No connect
29 NC
No connect
30 NC
No connect
Note 1 Relation between LVDS signals and actual data shows below section (4-2).
Note 2 The shielding case is connected with signal GND.
5 Page 
Quanta Display Inc.
(Hsync-Vsync Phase difference)
QD14XL2005 11 / 26
HV
Item(symbol)
Hsync-Vsync Phase difference
(THV)
Min.
1
Typ.
Max.
THA THC
Unit
clock
Remark
(Hsync-ENAB Phase difference)
HN
Item
(THN
Min.
0
Typ.
Max.
312
Unit Remark
clock
7-2 Display position
Item
Standards
Beginning
Horizontal rising edge of ENAB
0
rising edge of Hsync
296
Vertical rising edge of Vsync
35
Ending
1024
1320
803
Unit
clock
clock
clock
Remark
Note1
Note1 ENAB signal must be fixed to low.
Note
(Horizontal display direction)
When ENAB is fixed low, 296 clocks are counted from Hsync negative edge and
data from after are available. If you need other timing, please use ENAB signal.
(Vertical display direction)
35 lines are counted from Vsync negative edge and data from next line are
available.
Note of ENAB signal
ENAB could not be used for the purpose of the vertical display start timing.
Caution
Image will not be displayed on the right position otherwise.
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet QD14XL20.PDF ] | |
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