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부품번호 Z8000 기능
기능 Communications Controller
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Z8000 데이터시트, 핀배열, 회로
Zilog
Z8030 Z8000®
Z-SCC Serial
Communications Controller
Product
Specification
Features
General
Description
• Two independent, 0 to 1.5M bit/second, full-
duplex channels, each with a separate crystal
OSCillator, baud rate generator, and Digital
Phase-Locked Loop for clock recovery.
• Multi-protocol operation under program
control; programmable for NRZ, NRZI, or
FM data encoding.
• Asynchronous mode with five to eight bits
and one, one and one-half, or two stop bits
per character; programmable clock factor;
break detection and generation; parity,
overrun, and framing error detection.
• Synchronous mode with internal or external
character synchronization on one or two
The Z8030 Z-SCC Serial Communications
Controller is a dual-channel, multi-protocol
data communications peripheral designed for
use with the Zilog Z-Bus. The Z-SCC functions
as a serial-to-parallel, parallel-to-serial con-
verter/controller. The Z-SCC can be software-
configured to satisfy a wide variety of serial
April 1985
synchronous characters and CRC genera-
tion and checking with CRC-16 or
CRC-CCITT preset to either Is or Os.
• SDLC/HDLC mode with comprehensive
frame-level control, automatic zero insertion
and deletion, I-field residue handling, abort
generation and detection, CRC generation
and checking, and SDLC Loop mode
operation.
• Local Loopback and Auto Echo modes.
• 1.544M bit/second Tl digital trunk compatible
version available.
communications applications. The device con-
tains a variety of new, sophisticated internal
functions including on-chip baud rate
generators, Digital Phase-Locked Loops, and
crystal oscillators that dramatically reduce the
need for external logic.
2016-001,002
ADDRESS'
DATA BUS
AD,
TxDA
} SERIAL
AD, RIlOA _ _ DATA
AD, TRxCA ........-} CHANNEL
AD, RTxCA .--- CLOCKS
AD,
AD, CHANNEL
AD, CONTROLS
FOR MODEM,
ADo DMA,OR
As OTHER
OS
R/W
es,
} SERIAL
_ _ DATA
esc
INT
INTACK
lEI
lEO
-\IRTxes
._...._...
I\
CHANNEL
CLOCKS
SYNCe
WIREOB
DTR/REQB
RlSB
CHANNEL
CONTROLS
FDOMRAM,OORDEM,
Z8030 else __ OTHER
z·scc DeDS
CH·A
CH·B
ttt
+5V GND PCLK
Figure I. Pin Funcllons
AD,
AD,
AD,
AD,
iNT
lEO
lEi
INTACK
+sv
WIREQA
SYNCA
RheA
RIlOA
TRxCA
hDA
OTR/REQA
RlSA
elSA
DeCA
PClK
ADO
39 AD,
38 AD,
37 AD,
36 OS
35 As
34 RIW
Z8030
z·scc
11
33
32
31
30
eso
es,
GND
W/REoe
12 29 SYNCe
"13 RTxCB
37 RKOB
26 TRlleB
16 25 1)(D8
24 DTRIREQB
18 23 Rlse
19 22 elSS
21 DC De
Figure 2. 40-pin Dual-In-Line Package (DIP).
Pin Assignments
631




Z8000 pdf, 반도체, 판매, 대치품
Pin
Description
(Continued)
in Write Register 5 (Figure 11) is set, the RTS
signal goes Low. When the RTS bit is reset in the
Asynchronous mode and Auto Enable is on, the
signal goes High after the transmitter is empty. In
Synchronous mode or in Asynchronous mode
with Auto Enable off, the RTS pin strictly follows
the state of the RTS bit. Both pins can be used as
general-purpose outputs.
R/W. Read/Write (input). This signal specifies
whether the operation to be performed is a read
ora write.
SYNCA. SYNCB. Synchronization (inputs or
outputs, active Low). These pins can act either as
inputs, outputs, or part of the crystal oscillator
circuit.
In the Asynchronous Receive mode (crystal
oscillator option not selected), these pins are
inputs similar to CTS and DCD. In this mode,
transitions on these lines affect the state of the
Synchronous/Hunt status bits in Read Register 0
(Figure 10) but have no other function.
In External Synchronization mode with the
crystal oscillator not selected, these lines also act
as inputs. In this mode, SYNC must be driven
Low two receive clock cycles after the last bit in
the synchronous character is received. Character
assembly begins on the rising edge of the receive
clock immediately preceding the activation of
SYNC.
In the Internal Synchronization mode (Mono-
sync and Bisync) with the crystal oscillator not
selected, these pins act as outputs and are active
only during the part of the receive clock cycle in
which synchronous characters are recognized.
The synchronous condition is not latched, so
these outputs are active each time a synchroniza-
tion pattern is recognized (regardless of charac-
ter boundaries). In SDLC mode, these pins act as
outputs and are valid on receipt of a flag.
TxDA. TxDB. Transmit Data (outputs, active
High). These output signals transmit serial data
at standard TTL levels.
TRxCA. TRxCA. Transmit/Receive Clocks
(inputs or outputs, active Low). These pins can
be programmed in several different modes of
operation. TRxC may supply the receive clock
or the transmit clock in the input mode or supply
the output of the Digital Phase-Locked Loop, the
crystal oscillator, the baud rate generator, or the
transmit clock in the output mode.
W/REQA. W/REQB. Wait/Request (outputs,
active Low. Open-drain when programmed for a
Wait function; when programmed for a 3-state
Request function). These dual-purpose outputs
may be programmed as Request lines for a DMA
controller or as Wait lines to synchronize the
CPU to the Z-SCC data rate. The reset state is
Wait.
Functional
Description
The functional capabilities of the Z-SCC
can be described from two different points
of view: as a data communications device,
it transmits and receives data in a wide
variety of data communications protocols;
as a Z8000 Family peripheral, it interacts
with the Z8000 CPU and other peripheral
circuits and is part of the Z-Bus interrupt
structure.
Data Communications Capabilities. The
Z-SCC provides two independent full-duplex
channels programmable for use in any com-
mon Asynchronous or Synchronous data-
communication protocol. Figure 3 and the
following description briefly detail these
protocols.
Asynchronous Modes. Transmission and
reception can be accomplished independently
on each channel with five to eight bits per
character, plus optional even or odd parity.
The transmitters can supply one, one-and-a-
half, or two stop bits per character and can
provide a break output at any time. The
receiver break-detection logic interrupts the
CPU both at the start and at the end of a
received break. Reception is protected from
spikes by a transient spike-rejection
mechanism that checks the signal one-half a
!PARITY
STrT S~OP
I. .I'::-M':-::R~K'N::::G'7L1~NE~--'1 .I-.o-,T-,...,I""I""''"''.'...I...-_o-,_T=,=I=I...'"''...IO--0_,T_,.... i MARKING LINE
SYNC
DATA
SYNC
SYNC
DATA
SIGNAL
t
I DATA
ASYNCHRONOUS
:: I DATA
CRC1
CRC2
MONOSYNC
:: DATA
CRCl
CRC2
BISYNC
:: DATA
CRCl
CRC2
EXTERNAL SYNC
I IflAG
ADDRESS
lNFO{M~TlON
CRC1
CRC2
FLAG
SDLCIHDLCIX.25
Figure 3. Some Z-SCC Protocols
634
2016·004

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Z8000 전자부품, 판매, 대치품
Functional
Description
(Continued)
incoming data stream for edges (either 1 to 0
or 0 to 1). Whenever an edge is detected, the
OPLL makes a count adjustment (during the
next counting cycle). producing a terminal
count closer to the center of the bit cell.
For FM encoding, the OPLL still counts from
o to 31, but with a cycle corresponding to two
bit times. When the OPLL is locked, the clock
edges in the data stream should occur between
counts 15 and 16 and between counts 31 and
O. The OPLL looks for edges only during a
time centered on the 15 to 16 counting
transition.
The 32x clock for the OPLL can be pro-
grammed to come from either the RTxC input
or the output of the baud rate generator. The
OPLL output may be programmed to be
echoed out of the Z-SCC via the TRxC pin (if
this pin is not being used as an input).
Data Encoding The Z-SCC may be pro-
grammed to encode and decode the serial data
in four different ways (Figure 6). In NRZ
encoding, a 1 is represented by a High level
and a 0 is represented by a Low level. In NRZI
encoding, a 1 is represented by no change in
level and a 0 is represented by a change in
level. In FMl (more properly, bi-phase mark)
a transition occurs at the beginning of every
bit cell. A 1 is represented by an additional
transition at the center of the bit cell and a 0 is
represented by no additional transition at the
center of the bit cell. In FMO (bi-phase space).
a transition occurs at the beginning of every
bit cell. A 0 is represented by an additional
transition at the center of the bit cell, and a 1
is represented by no additional transition at
the center of the bit cell. In addition to these
four methods, the Z-SCC can be used to
decode Manchester (bi-phase level) data by
using the OPLL in the FM mode and program-
ming the receiver for NRZ data. Manchester
encoding always produces a transition at the
center of the bit cell. If the transition is 0 to 1,
the bit is a O. If the transition is 1 to 0 the
bit is a 1.
Auto Echo and Local Loopback. The Z-SCC
is capable of automatically echoing everything
it receives. This feature is useful mainly in
Asynchronous modes, but works in Syn-
chronous and SOLC modes as well. In Auto
Echo mode, TxO is RxO. Auto Echo mode can
be used with NRZI or FM encoding with no
additional delay, because the data stream is
not decoded before retransmission. In Auto
Echo mode, the CTS input is ignored as a
transmitter enable (although transitions on this
input can still cause interrupts if programmed
to do so). In this mode, the transmitter is
actually bypassed and the programmer is
responsible for disabling transmitter interrupts
and WAIT/REQUEST on transmit.
The Z-SCC is also capable of Local Loop-
back. In this mode TxO is RxO, just as in Auto
Echo mode. However, in Local Loopback
mode, the internal transmit data is tied to the
internal receive data and RxO is ignored
(except to be echoed out via TxO). The CTS
and OCO inputs are also ignored as transmit
and receive enables. However, transitions on
these inputs can still cause interrupts. Local
Loopback works in Asynchronous, Syn-
chronous and SOLC modes with NRZ, NRZI or
FM coding of the data stream.
I/O Interface Capabilities. The Z-SCC offers
the choice of Polling, Interrupt (vectored or
nonvectored) , and Block Transfer modes to
transfer data, status, and control information to
and from the CPU. The Block Transfer mode
can be implemented under CPU or OMA
control.
Polling. All interrupts are disabled. Three
status registers in the Z-SCC are automatically
updated whenever any function is performed.
For example, end-of-frame in SOLC mode
sets a bit in one of these status registers. The
idea behind polling is for the CPU to period-
ically read a status register until the register
contents indicate the need for data to be
transferred. Only one register needs to be
2016·007
Figure 6. Data Encoding Methods
637

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관련 데이터시트

부품번호상세설명 및 기능제조사
Z8000

Communications Controller

Zilog
Zilog
Z8001AB1V

CENTRAL PROCESSING UNIT

STMicroelectronics
STMicroelectronics

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