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KSZ8041RNL 데이터시트 PDF




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부품번호 KSZ8041RNL 기능
기능 10Base-T/100Base-TX Physical Layer Transceiver
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KSZ8041RNL 데이터시트, 핀배열, 회로
KSZ8041NL/RNL
10Base-T/100Base-TX
Physical Layer Transceiver
Revision 1.5
General Description
The KSZ8041NL is a single supply 10Base-T/100Base-TX
physical layer transceiver, which provides MII/RMII
interfaces to transmit and receive data. A unique mixed
signal design extends signaling distance while reducing
power consumption.
HP Auto MDI/MDI-X provides the most robust solution for
eliminating the need to differentiate between crossover
and straight-through cables.
The KSZ8041NL represents a new level of features and
performance and is an ideal choice of physical layer
transceiver for 10Base-T/100Base-TX applications.
The KSZ8041RNL is an enhanced RMII version of the
KSZ8041NL that does not require a 50MHz system clock.
It uses a 25MHz crystal for its input reference clock and
outputs a 50MHz RMII reference clock to the MAC.
The KSZ8041NL and KSZ8041RNL are available in 32-
pin, lead-free QFN packages (see Ordering Information).
Datasheets and support documentation are available on
Micrel’s web site at: www.micrel.com.
Functional Diagram
KSZ8041NL
TX+ 10/100
Transmitter Pulse
TX- Shaper
REXT
Adaptive EQ
RX+ Base Line
Wander Correction
RX- MLT3 Decoder
NRZI/NRZ
10Base-T
Receiver
NRZ/NRZI
MLT3 Encoder
4B/5B Encoder
Scrambler
Parallel/Serial
Parallel/Serial
Manchester Encoder
Clock
Recovery
4B/5B Decoder
Descrambler
Serial/Parallel
Auto
Negotiation
Manchester Decoder
Serial/Parallel
MDC
MDIO
TX_EN
TXD1
TXD0
RMII CRS_DV
RXD1
RXD0
RX_ER
REF_CLK
INTRP
XI
PLL
XO
Power Down
Power Saving
RST#
LED LED0
Driver LED1
KSZ8041RNL
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
February 4, 2015
Revision 1.5




KSZ8041RNL pdf, 반도체, 판매, 대치품
Micrel, Inc.
KSZ8041NL/RNL
Revision History
Revision
1.0
1.1
1.2
1.3
1.4
1.5
Date
10/13/06
4/27/07
7/18/08
12/11/09
1/19/10
2/2/15
Summary of Changes
Data sheet created.
Added maximum MDC clock speed.
Added 40K ±30% to Note 1 of Pin Description and Strapping Options tables for internal pull-ups/pull-
downs.
Changed Model Number in Register 3h – PHY Identifier 2.
Changed polarity (swapped definition) of DUPLEX strapping pin.
Removed DUPLEX strapping pin update to Register 4h – Auto-Negotiation Advertisement bits [8, 6].
Set “Disable power saving” as the default for Register 1Fh bit [10].
Corrected LED1 (pin 31) definition for Activity in LED mode 01.
Added Symbol Error to MII/RMII Receive Error description and Register 15h – RXER Counter.
Added a 100pF capacitor on REXT (pin 10) in Pin Description table.
Added Automotive Qualified part number to Ordering Information.
Added maximum case temperature.
Added thermal resistance (θJC).
Added chip maximum current consumption.
Added Automotive Qualified part number, KSZ8041NL EAM, to Ordering Information.
Changed MDIO hold time (min) from 10ns to 4ns.
Added LED drive current.
Renamed Register 3h bits [3:0] to “manufacturer’s revision number” and changed default value to
“Indicates silicon revision.”
Updated RMII output delay for CRSDV and RXD[1:0] output pins.
Added support for Asymmetric PAUSE in register 4h bit [11].
Added control bits for 100Base-TX preamble restore (register 14h bit [7]) and 10Base-T preamble restore
(register 14h bit [6]).
Changed strapping pin definition for CONFIG[2:0] = 100 from “PCS Loopback” to “MII 100Mbps Preamble
Restore.”
Corrected MII timing for tRLAT, tCRS1, tCRS2.
Added KSZ8041RNL device and updated entire data sheet accordingly.
Removed part number (KSZ8041NL EAM) from Ordering Information.
Removed chip maximum current consumption.
Added automotive qualified part number, KSZ8041RNLU.
Changed VDDPLL_1.8 (Pin 2) decoupling capacitor value from 10µF to 1.0µF.
Specified minimum 250µs rise time for 3.3V input supply voltages (VDDIO_3.3, VDDA_3.3).
Add the part numbers of the silver wire bonding in Ordering Information.
February 4, 2015
4
Revision 1.5

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KSZ8041RNL 전자부품, 판매, 대치품
Micrel, Inc.
KSZ8041NL/RNL
List of Figures
Figure 1. Auto-Negotiation Flow Chart................................................................................................................................ 22
Figure 2. KSZ8041NL RMII Interface.................................................................................................................................. 27
Figure 3. KSZ8041RNL RMII Interface ............................................................................................................................... 28
Figure 4. Typical Straight Cable Connection ...................................................................................................................... 29
Figure 5. Typical Crossover Cable Connection .................................................................................................................. 29
Figure 6. 25MHz Crystal/Oscillator Reference Clock ......................................................................................................... 30
Figure 7. 50MHz Oscillator Reference Clock fo KSZ8041NL RMII Mode .......................................................................... 30
Figure 8. KSZ8041NL/RNL Power and Ground Connections............................................................................................. 31
Figure 9. MII SQE Timing (10Base-T) ................................................................................................................................ 44
Figure 10. MII Transmit Timing (10Base-T) .......................................................................................................................... 45
Figure 11. MII Receive Timing (10Base-T) ........................................................................................................................... 46
Figure 12. MII Transmit Timing (100Base-TX)...................................................................................................................... 47
Figure 13. MII Receive Timing (100Base-TX)....................................................................................................................... 48
Figure 14. RMII Timing – Data Received from RMII ............................................................................................................. 49
Figure 15. RMII Timing – Data Input to RMII ........................................................................................................................ 49
Figure 16. Auto-Negotiation Fast Link Pulse (FLP) Timing .................................................................................................. 50
Figure 17. MDC/MDIO Timing............................................................................................................................................... 51
Figure 18. Power-Up/Reset Timing....................................................................................................................................... 52
Figure 19. Recommended Reset Circuit ............................................................................................................................... 53
Figure 20. Recommended Reset Circuit for interfacing with CPU/FPGA Reset Output....................................................... 53
Figure 21. Reference Circuits for LED Strapping Pins ......................................................................................................... 54
February 4, 2015
7
Revision 1.5

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부품번호상세설명 및 기능제조사
KSZ8041RNL

10Base-T/100Base-TX Physical Layer Transceiver

Micrel Semiconductor
Micrel Semiconductor

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