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CS4328 데이터시트 PDF




Crystal Semiconductor에서 제조한 전자 부품 CS4328은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 CS4328 자료 제공

부품번호 CS4328 기능
기능 Stereo D/A Converter
제조업체 Crystal Semiconductor
로고 Crystal Semiconductor 로고


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CS4328 데이터시트, 핀배열, 회로
CS4328
18-Bit, Stereo D/A Converter for Digital Audio
Features
General Description
Complete Stereo DAC System
8× Interpolation Filter
64× Delta-Sigma DAC
Analog Post Filter
Adjustable System Sampling Rates
including 32kHz, 44.1kHz & 48kHz
120 dB Signal-to-Noise Ratio
Low Clock Jitter Sensitivity
Completely Filtered Line-Level Outputs
Linear Phase Filtering
Zero Phase Error Between Channels
No External Components Needed
Flexible Serial Interface for Either 16
or 18 bit Input Data
The CS4328 is a complete stereo digital-to-analog out-
put system. In addition to the traditional D/A function,
the CS4328 includes an 8× digital interpolation filter fol-
lowed by a 64× oversampled delta-sigma modulator.
The modulator output controls the reference voltage in-
put to an ultra-linear analog low-pass filter. This
architecture allows for infinite adjustment of sample
rate between 1 kHz and 50 kHz while maintaining lin-
ear phase response simply by changing the master
clock frequency.
The CS4328 also includes an extremely flexible serial
port utilizing two select pins to support four different
interface modes.
The master clock can be either 256 or 384 times the
input word rate, supporting various audio environ-
ments.
ORDERING INFORMATION:
CS4328-KP
0 to 70 °C
28-pin Plastic DIP
CS4328-KS
0 to 70 °C
28-pin Plastic SOIC
CS4328-BP
-40 to +85 °C 28-pin Plastic DIP
CS4328-BS
-40 to +85 °C 28-pin Plastic SOIC
CDB4328
CS4328 Evaluation Board
LRCK
BICK
SDATAI
20
19
18
DIF0
13
DIF1
12
Serial Input
Interface
TST
RST
10
9
8x
Interpolator
IInntteerrpp8ooxllaattoorr
Calibration
Microcontroller
21
CALO
8
CMPI
VD+
16
DGND
17
DDMMeelloottaadd--uuSSllaaiiggttoommrraa
S DDMMeelloottaadd--uuSSllaaiiggttoommrraa
R Clock Osc/
A Divider
M
14 15 11 22
XTI XTO CKS ACKO
AGND1 VA- VA+
1 53
Voltage Reference
DAC
Analog
Low-Pass
Filter
MOSFET
Output
Stage
DAC
Analog
Low-Pass
Filter
MOSFET
Output
Stage
24
ACKI
27
CALI
6
CMPO
28
-VREF
2
AOUTL
26
AOUTR
4
AGND2
25
AGND3
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 FAX: (512) 445-7581
http://www.crystal.com
Copyright © Crystal Semiconductor Corporation 1993
(All Rights Reserved)
OCT ’93
DS62F3
1




CS4328 pdf, 반도체, 판매, 대치품
CS4328
SWITCHING CHARACTERISTICS
(TA = 25 °C; VA+, VD+ = 5V ± 5%; VA- = -5V ± 5%; Inputs: Logic 0 = 0V, Logic 1 = VD+, CL = 20 pF)
Parameter
Symbol
Min
Typ
Max Units
Master Clock Frequency using Internal Oscillator:
CKS=H
CKS=L
XTI/XTO
10.7
-
19.2 MHz
- 7.1 - 13.9 MHz
Master Clock Frequency using External Clock:
CKS=H
CKS=L
XTI/XTO
-
0.384
0.256
-
-
19.2 MHz
13.9 MHz
XTI/XTO Pulse Width Low
- 21 - - ns
XTI/XTO Pulse Width High
- 21 - - ns
BICK Pulse Width Low
BICK Pulse Width High
BICK Period
BICK rising to LRCK edge delay
BICK rising to LRCK edge setup time
SDATAI valid to BICK rising setup time
BICK rising to SDATAI hold time
RST Minimum Pulse Width Low
(Note 6)
(Note 6)
(Note 6)
(Note 6)
tbickl
30
-
tbickh
30
-
tbickw
80
-
tblrd 35
-
tblrs 35
-
tsbs 35 -
tbsh 35
-
2 periods of XTI/XTO
- ns
- ns
- ns
- ns
- ns
- ns
- ns
Note: 6. "BICK rising" refers to modes 0, 1, and 3. For mode 2, replace "BICK rising" with "BICK falling."
LRCK
BICK
SDATAI
t blrd
t sbs
t blrs
tbickl tbickh
t bsh
Serial Input Timing (Modes 0, 1, &3)
LRCK
BICK
SDATAI
t blrd
t blrs
tbickl tbickh
tsbs tbsh
MSB
MSB-1
Serial Input Timing (Mode 2)
4 DS62F3

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CS4328 전자부품, 판매, 대치품
CS4328
RST
LRCK
"Kickstart"
XTI/XTO
ACK0
40 ns
minimum
40 ns
minimum
Reset Status
Exit Reset
Figure 2. RESET Cancellation Timing
latch data. Table 2 lists the four formats, along
with the associated figure number. Format 0 is
compatible with existing 16-bit D/A converters
and digital filters. Format 1 is an 18-bit version
of format 0. Format 2 is similar to Crystal ADCs
and many DSP serial ports. Format 3 is compat-
ible with the I2S serial data protocol. Formats 2
and 3 support 18-bit input or 16-bit followed by
two zeros. In all four serial input modes, the se-
rial data is MSB-first and 2’s-complement
format.
Formats 0, 2 and 3 will operate with 16-bit data
and 16 BICK pulses as well. See Figure 6 for
16-bit timing. However, the use of
BICK = 64× IWR is recommended to minimize
the possibility of performance degradation result-
ing from BICK coupling into VREF-.
DIF1
0
0
1
1
DIF0
0
1
0
1
Mode
0
1
2
3
Figure
3
3
4
5
Table 2. Digital Input Formats
Reset and Offset Calibration
RST is an active low signal that resets the digital
filter and the delta-sigma modulator, synchro-
nizes LRCK with internal control signals and
starts an offset calibration cycle upon exiting re-
set. When RST goes low, CALO goes high and
stays high until the end of an offset calibration
cycle. An offset calibration cycle takes 1024
IWR cycles to complete. CALO must be con-
nected to CALI and CMPO must be connected
to CMPI for offset calibration. During an offset
calibration the analog output is forced to zero.
Power-Up Considerations
Upon initial application of power to the DAC,
offset calibration and digital filter registers will
be indeterminate. RST should be low during
power-up to activate an internal mute and pre-
vent this erroneous information from being
output from the DAC. Bringing RST high will
begin a calibration cycle and initialize these reg-
isters.
Muting
There are two types of mutes that can be imple-
mented with the CS4328. The first is a -50 dB
DS62F3
7

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