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PDF CS4327 Data sheet ( Hoja de datos )
| Número de pieza | CS4327 | |
| Descripción | 20-Bit Stereo Audio D/A Converter | |
| Fabricantes | Crystal Semiconductor | |
| Logotipo |  |
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CS4327
Low Cost, 20-Bit, Stereo, Audio D/A Converter
Features
l 20-Bit Conversion
l 108 dB Signal-to-Noise-Ratio (EIAJ)
l 100 dB Dynamic Range
l Single-Ended Outputs
l Complete Stereo DAC System
- 128X Interpolation Filter
- Delta-Sigma DAC
- Analog Post Filter
l Low Clock Jitter Sensitivity
l Filtered Line-Level Outputs
- Linear Phase Filtering
- Zero Phase Error Between Channels
l Digital De-emphasis for 32 kHz, 44.1 kHz &
48 kHz
I
Description
The CS4327 is a complete stereo digital-to-analog out-
put system. In addition to the traditional D/A function, the
CS4327 includes a digital interpolation filter followed by
an 128X oversampled delta-sigma modulator. The mod-
ulator output controls the reference voltage input to an
ultra-linear analog low-pass filter. This architecture al-
lows for infinite adjustment of sample rate between 1 and
50 kHz while maintaining linear phase response simply
by changing the master clock frequency.
The CS4327 also includes an extremely flexible serial
port utilizing mode select pins to support multiple inter-
face formats.
The master clock can be either 256, 384, or 512 times
the input sample rate, supporting various audio
environments.
ORDERING INFO
CS4327-KS -10 to 70 °C 16-pin Plastic SSOP
CDB4327 CS4327 Evaluation Board
LRCK 7
SCLK 9
SDATA 10
DIF0 DIF1
15 11
Serial Input
Interface
DEM0 DEM1
12
De-emphasis
VA+ VD+
36
Voltage Reference
16 CMFILT
Interpolator
AUTO_MUTE 12
Interpolator
5
DGND
Delta-Sigma
Modulator
Delta-Sigma
Modulator
8
MCLK
DAC
DAC
4
AGND
Analog
Low-Pass
Filter
14 AOUTL
Analog
Low-Pass
Filter
13 AOUTR
Cirrus Logic, Inc.
Crystal Semiconductor Products Division
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.crystal.com
Copyright © Cirrus Logic, Inc. 1997
(All Rights Reserved)
DEC ‘97
DS190F1
1
1 page  
LRCK
SCLK
SDATA
t slrd
t slrs
t sclkl t sclkh
t sdlrs
t sdh
External Serial Mode Input Timing
LRCK
t sclkr
SDATA
t sdlrs t sdh
t sclkw
*INTERNAL SCLK
Internal Serial Mode Input Timing.
* The SCLK pin must be terminated to ground.
The SCLK pulses shown are internal to the CS4327
CS4327
DS190F1
5
5 Page 
CS4327
clock routing on the printed circuit board can de-
grade system performance. The use of the internal
serial clock mode simplifies the routing of the
printed circuit board by allowing the serial clock
trace to be deleted and avoids possible interference
effects.
Auto Mute
An auto-mute function is useful for applications,
such as compact disk players, where the idle chan-
nel noise must be minimized. The CS4327 will au-
tomatically initiate a mute for an idle channel input,
where idle channel is defined as an input of static
1’s or static 0’s during 8192 consecutive LRCK cy-
cles. The mute will be immediately released when
non-idle channel data is applied to either the Left or
Right channels. This feature is selectable and active
only if the AUTO_MUTE pin is low.
De-Emphasis
Implementation of digital de-emphasis requires re-
configuration of the digital filter to maintain the fil-
ter response shown in Figure 6 at multiple sample
rates. The CS4327 is capable of digital de-empha-
sis for 32, 44.1 or 48 kHz sample rates. Table 3
shows the de-emphasis control inputs for DEM 0
and DEM 1.
Gain
dB
0 dB
T1=50 µs
-10 dB
T2 = 15 µs
DEM1
0
0
1
1
DEM0
0
1
0
1
De-emphasis
32 kHz
44.1 kHz
48 kHz
OFF
Table 3. De-Emphasis Filter Selection
Initialization, Calibration and Power-Down
Upon initial power-up, the DAC enters the power-
down mode. The interpolation filters and delta-sig-
ma modulators are reset, and the internal voltage
reference, one-bit D/A converters and switched-ca-
pacitor low-pass filters are powered down. The de-
vice will remain in the power-down mode until
MCLK and LRCK are presented. Once MCLK and
LRCK are detected, MCLK occurrences are count-
ed over one LRCK period to determine the MCLK
/ LRCK frequency ratio. Power is applied to the in-
ternal voltage reference, the D/A converters,
switched-capacitor filters and the DAC will begin a
common mode bias voltage calibration. This ini-
tialization and calibration sequence requires ap-
proximately 2700 cycles of LRCK. The CS4327
will enter the power-down mode, within 1 period of
LRCK, if either MCLK or LRCK is removed. The
initialization sequence, as described above, occurs
when MCLK and LRCK are restored.
An offset calibration can be invoked by changing
the state of Digital Input Format pins, DIF0 and/or
DIF1, for at least 3 LRCK cycle. During calibra-
tion, a common-mode voltage of approximately
1.8 V appears at the outputs, with approximately a
16 kohm output impedance. Following calibration,
the analog output impedance becomes less than
10 ohms and the common mode voltage will move
to approximately 2.3 V.
F1
3.183 kHz
F2 Frequency
10.61 kHz
Figure 6. De-emphasis Filter Response
DS190F1
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11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CS4327.PDF ] | |
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