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PDF CS4329 Data sheet ( Hoja de datos )
| Número de pieza | CS4329 | |
| Descripción | 20-Bit Stereo D/A Converter | |
| Fabricantes | Crystal Semiconductor | |
| Logotipo |  |
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CS4329
20-Bit, Stereo D/A Converter for Digital Audio
Features
l 20-Bit Conversion
l 115 dB Signal-to-Noise-Ratio (EIAJ)
l Complete Stereo DAC System
- 128X Interpolation Filter
- Delta-Sigma DAC
- Analog Post Filter
l 106 dB Dynamic Range
l Low Clock Jitter Sensitivity
l Filtered Line-Level Outputs
- Linear Phase Filtering
- Zero Phase Error Between Channels
l Adjustable System Sampling Rates
- including 32 kHz, 44.1 kHz & 48 kHz
l Digital De-emphasis for 32 kHz, 44.1 kHz, &
48 kHz
l Pin-compatible with the CS4390
I
Description
The CS4329 is a complete stereo digital-to-analog out-
put system. In addition to the traditional D/A function, the
CS4329 includes a digital interpolation filter followed by
an 128X oversampled delta-sigma modulator. The mod-
ulator output controls the reference voltage input to an
ultra-linear analog low-pass filter. This architecture al-
lows for infinite adjustment of sample rate between 1 and
50 kHz while maintaining linear phase response simply
by changing the master clock frequency.
The CS4329 also includes an extremely flexible serial
port utilizing mode select pins to support multiple inter-
face formats.
The master clock can be either 256, 384, or 512 times
the input sample rate, supporting various audio
environments.
ORDERING INFORMATION
CS4329-KP -10° to 70° C
CS4329-KS -10° to 70° C
CDB4329
20-pin Plastic DIP
20-pin Plastic SSOP
Evaluation Board
7
LRCK
9
SCLK
10
SDATA
DIF0 DIF1 DIF2
20 19 12
Serial Input
Interface
DEM0 DEM1
12
De-emphasis
VA VD
36
Voltage Reference
MUTE_L
16
Interpolator
Delta-Sigma
Modulator
AUTO_MUTE 11
Interpolator
5
DGND
Delta-Sigma
Modulator
8
MCLK
DAC
DAC
4
AGND
Analog
Low-Pass
Filter
AOUTL+
18
AOUTL-
17
Analog
Low-Pass
Filter
15
MUTE_R
AOUTR+
14
AOUTR-
13
Cirrus Logic, Inc.
Crystal Semiconductor Products Division
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.crystal.com
Copyright © Cirrus Logic, Inc. 1998
(All Rights Reserved)
APR ‘98
DS153F1
1
1 page  
CS4329
DIGITAL CHARACTERISTICS (TA = 25°C; VD = 5 V ±5%)
Parameter
High-Level Input Voltage
Low-Level Input Voltage
Input Leakage Current
Digital Input Capacitance
Symbol Min
Typ
Max Unit
VIH 2.0
-
-V
VIL - - 0.8 V
Vin -
-
±10.0
µA
- 10 - pF
ABSOLUTE MAXIMUM RATINGS (AGND = 0 V, all voltages with respect to ground.)
Parameter
DC Power Supply:
Positive Analog
Positive Digital
|VA - VD|
Input Current, Any Pin Except Supplies
Digital Input Voltage
Ambient Operating Temperature (power applied)
Storage Temperature
Symbol
Min
Max
VA -0.3 6.0
VD -0.3 6.0
0.0 0.4
Iin
VIND
TA
Tstg
- ±10
-0.3 (VD)+0.4
-55 125
-65 150
Unit
V
V
V
mA
V
°C
°C
WARNING: Operation at or beyond these limits may result in permanent damage to the device.Normal operation is
not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS (DGND = 0V; all voltages with respect to ground)
DC Power Supply:
Parameter
Positive Digital
Positive Analog
|VA - VD|
Symbol
VD
VA
Min
4.75
4.75
-
Typ
5.0
5.0
-
Max
5.25
5.25
0.4
Unit
V
V
V
DS153F1
5
5 Page 
CS4329
Serial Clock
The serial clock controls the shifting of data into
the input data buffers. The CS4329 supports both
external and internal serial clock generation modes.
External Serial Clock
The CS4329 will enter the external serial clock
mode if 15 or more high\low transitions are detect-
ed on the SCLK pin during any phase of the LRCK
period. When this mode is enabled, internal serial
clock mode cannot be accessed without returning
to the power down mode.
Internal Serial Clock
In the Internal Serial Clock Mode, the serial clock
is internally derived and synchronous with MCLK.
The internal SCLK / LRCK ratio is always 64 and
operation in this mode is identical to operation with
an external serial clock synchronized with LRCK.
The SCLK pin must be connected to DGND for
proper operation.
The internal serial clock mode is advantageous in
that there are situations where improper serial
clock routing on the printed circuit board can de-
grade system performance. The use of the internal
serial clock mode simplifies the routing of the
printed circuit board by allowing the serial clock
trace to be deleted and avoids possible interference
effects.
Mute Functions
The CS4329 includes an auto-mute function which
will initiate a mute if 8192 consecutive 0’s or 1’s are
input on both the Left and Right channels. The
mute will be released when non-static input data is
applied to the DAC. The auto-mute function is use-
ful for applications, such as compact disk players,
where the idle channel noise must be minimized.
This feature is active only if the AUTO_MUTE pin
is low and is independent of the status of MUTE_L
and MUTE_R. Either channel can also be muted
instantaneously with the MUTE_L or MUTE_R.
De-Emphasis
Implementation of digital de-emphasis requires re-
configuration of the digital filter to maintain the fil-
ter response shown in Figure 8 at multiple sample
rates. The CS4329 is capable of digital de-empha-
sis for 32, 44.1 or 48kHz sample rates. Table 3
shows the de-emphasis control inputs for DEM 0
and DEM 1.
DEM 1
0
0
1
1
DEM 0
0
1
0
1
De-emphasis
32 kHz
44.1 kHz
48 kHz
OFF
Table 3. De-Emphasis Filter Selection
Gain
dB
T1=50µs
0dB
-10dB
T2 = 15µs
F1
3.183 kHz
F2 Frequency
10.61 kHz
Figure 8. De-emphasis Filter Response
Initialization, Calibration and Power-Down
Upon initial power-up, the DAC enters the power-
down mode. The interpolation filters and delta-sig-
ma modulators are reset, and the internal voltage
reference, one-bit D/A converters and switched-ca-
pacitor low-pass filters are powered down. The de-
vice will remain in the power-down mode until
MCLK and LRCK are presented. Once MCLK and
LRCK are detected, MCLK occurrences are count-
ed over one LRCK period to determine the
MCLK/LRCK frequency ratio. The phase and fre-
quency relationship between the two clocks must
remain fixed. If during any LRCK this relationship
DS153F1
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CS4329.PDF ] | |
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